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White Rabbit core collection
Commit b6dfc740 authored by Dimitris Lampridis's avatar Dimitris Lampridis Committed by Maciej Lipinski
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hdl: use dual reset async fifos and pulse synchronizers to help with meeting timing (re-done) 

Second attempt to use dual reset async fifos and pulse synchronizers. The first one was 9810ef9a,
later on reverted by 93d49e1f, because it was causing sync problems when unplugging/replugging the
fiber.

The problem was in the endpoint's rx path, where one side of the reset (the rx_clk side) was taking
into account the state of the PHY (via the phy_rdy_i signal), while the other side (the sys_clk
side) was not. This has been fixed in this commit, by using phy_rdy_i as an active-low reset source
for both clock domains of the rx path.

Tested on an SPEC, works.
parent 97e35b72
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Showing with 1444 additions and 1725 deletions
general-cores @ ea05c883
Subproject commit c2352830d433e3fb3cf75a24bb60bf2d02393397
Subproject commit ea05c88360e5cb82450aa9205db655876d8aa4db
modules/timing/dmtd_with_deglitcher.vhd
View file @ b6dfc740
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-02-25
-- Last update: 2014-07-15
-- Last update: 2018-10-25
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
......@@ -164,14 +164,15 @@ begin -- rtl
data_i => resync_p_a_i,
synced_o => resync_p_dmtd);
U_Sync_Start_Pulse : gc_pulse_synchronizer
U_Sync_Start_Pulse : gc_pulse_synchronizer2
port map (
clk_in_i => clk_sys_i,
clk_out_i => clk_dmtd_i,
rst_n_i => rst_n_dmtdclk_i,
d_ready_o => open,
d_p_i => resync_start_p_i,
q_p_o => resync_start_p_dmtd);
clk_in_i => clk_sys_i,
rst_in_n_i => rst_n_sysclk_i,
clk_out_i => clk_dmtd_i,
rst_out_n_i => rst_n_dmtdclk_i,
d_ready_o => open,
d_p_i => resync_start_p_i,
q_p_o => resync_start_p_dmtd);
U_Sync_Resync_Done : gc_sync_ffs
generic map (
......
modules/wr_endpoint/ep_clock_alignment_fifo.vhd
View file @ b6dfc740
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2012-08-28
-- Last update: 2018-10-25
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -84,7 +84,7 @@ begin
f_pack_fifo_contents (fab_i, fifo_in, fifo_we, false);
-- Clock adjustment FIFO
U_FIFO : generic_async_fifo
U_FIFO : generic_async_fifo_dual_rst
generic map (
g_data_width => 18,
g_size => g_size,
......@@ -92,12 +92,13 @@ begin
g_almost_full_threshold => g_almostfull_threshold
)
port map (
rst_n_i => rst_n_wr_i,
rst_wr_n_i => rst_n_wr_i,
clk_wr_i => clk_wr_i,
d_i => fifo_in,
we_i => fifo_we,
wr_full_o => full_o,
wr_almost_full_o => almostfull_o,
rst_rd_n_i => rst_n_rd_i,
clk_rd_i => clk_rd_i,
q_o => fifo_out,
rd_i => rx_rdreq,
......
modules/wr_endpoint/ep_packet_filter.vhd
View file @ b6dfc740
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2017-02-02
-- Last update: 2018-10-25
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -360,12 +360,13 @@ begin -- behavioral
end if;
end process;
U_Sync_Done : gc_pulse_synchronizer
U_Sync_Done : gc_pulse_synchronizer2
port map (
clk_in_i => clk_rx_i,
clk_out_i => clk_sys_i,
rst_n_i => rst_n_rx_i,
d_p_i => done_int,
q_p_o => done_o);
clk_in_i => clk_rx_i,
rst_in_n_i => rst_n_rx_i,
clk_out_i => clk_sys_i,
rst_out_n_i => rst_n_sys_i,
d_p_i => done_int,
q_p_o => done_o);
end behavioral;
modules/wr_endpoint/wr_endpoint.vhd
View file @ b6dfc740
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-04-26
-- Last update: 2018-03-08
-- Last update: 2018-10-25
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -436,7 +436,13 @@ architecture syn of wr_endpoint is
signal pcs_rmon : t_rmon_triggers;
signal rx_path_rmon : t_rmon_triggers;
signal rmon : t_rmon_triggers;
-------------------------------------------------------------------------------
-- Synchronisation for RX path
-------------------------------------------------------------------------------
signal phy_rdy_resync_sys : std_logic;
signal rst_n_rx_resync_sys : std_logic;
-------------------------------------------------------------------------------
-- chipscope (for desperates)
-------------------------------------------------------------------------------
......@@ -460,8 +466,19 @@ architecture syn of wr_endpoint is
begin
U_Sync_phy_rdy_sysclk : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => phy_rdy_i,
synced_o => phy_rdy_resync_sys);
rst_n_rx <= rst_rxclk_n_i and phy_rdy_i;
rst_n_rx_resync_sys <= rst_sys_n_i and phy_rdy_resync_sys;
-------------------------------------------------------------------------------
-- 1000Base-X PCS
-------------------------------------------------------------------------------
......@@ -609,7 +626,7 @@ begin
clk_sys_i => clk_sys_i,
clk_rx_i => phy_rx_clk_i,
rst_n_sys_i => rst_sys_n_i,
rst_n_sys_i => rst_n_rx_resync_sys,
rst_n_rx_i => rst_n_rx,
pcs_fab_i => rxpath_fab,
......
syn/spec_ref_design/Makefile
View file @ b6dfc740
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syn/spec_ref_design/spec_wr_ref.xise
View file @ b6dfc740
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