adding Vivado project to generate wrc_board_fasec IPcore

930f334c · Grzegorz Daniluk · 767f450b · 930f334c · 930f334c · 930f334c
Commit 930f334c authored Aug 18, 2017 by Grzegorz Daniluk
6 changed files
--- a/.gitignore
+++ b/.gitignore
@@ -17,3 +17,5 @@ doc/
 *.elf
 *.ucdb
 Makefile
+*.xml
+xgui/
--- a/board/fasec/component.xml
+++ b/board/fasec/component.xml
--- a/syn/wrc_board_fasec_ipcore/Manifest.py
+++ b/syn/wrc_board_fasec_ipcore/Manifest.py
@@ -6,7 +6,7 @@ syn_grade = "-2"
 syn_package = "ffg676"
 syn_top = "wrc_board_fasec"
-syn_project = "fasec_wr_ref_top"
+syn_project = "wrc_board_fasec_ip"
 syn_tool = "vivado"

--- a/syn/wrc_board_fasec_ip/README.txt
+++ b/syn/wrc_board_fasec_ip/README.txt
+To create Vivado project for wrc_board_fasec IPcore generation, open Vivado and
+run build.tcl script.
--- a/syn/wrc_board_fasec_ip/build.tcl
+++ b/syn/wrc_board_fasec_ip/build.tcl
+# Copy component.xml
+file copy -force ../../board/fasec/component.xml ../../.
+# Run tcl script generated by Vivado
+source ./wrc_board_fasec_ip.tcl
--- a/syn/wrc_board_fasec_ip/wrc_board_fasec_ip.tcl
+++ b/syn/wrc_board_fasec_ip/wrc_board_fasec_ip.tcl