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White Rabbit core collection
Commits
92c269b1
Commit
92c269b1
authored
Jul 04, 2017
by
Grzegorz Daniluk
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modules/wrc_core: cleanup
parent
76741ddb
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6 changed files
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98 additions
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133 deletions
+98
-133
wb_reset.vhd
modules/wrc_core/wb_reset.vhd
+0
-97
wr_core.vhd
modules/wrc_core/wr_core.vhd
+4
-12
wrc_periph.vhd
modules/wrc_core/wrc_periph.vhd
+22
-8
wrcore_pkg.vhd
modules/wrc_core/wrcore_pkg.vhd
+34
-0
xwr_core.vhd
modules/wrc_core/xwr_core.vhd
+16
-9
xwr_syscon_wb.vhd
modules/wrc_core/xwr_syscon_wb.vhd
+22
-7
No files found.
modules/wrc_core/wb_reset.vhd
deleted
100644 → 0
View file @
76741ddb
-------------------------------------------------------------------------------
-- Title : WhiteRabbit PTP Core ZPU reset generator
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wb_reset.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-04-04
-- Last update: 2011-10-29
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- WB_RESET is a reset signal generator for ZPU. It is controlled by wishbone
-- and is used by ZPU firmware loader(zpu-loader) to reset the processor during
-- copying the binary to dpram.
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Grzegorz Daniluk
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-04-04 1.0 greg.d Created
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
entity
wb_reset
is
port
(
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
rst_cpu_n_o
:
out
std_logic
;
rst_net_n_o
:
out
std_logic
;
wb_addr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_data_i
:
in
std_logic_vector
(
31
downto
0
);
wb_data_o
:
out
std_logic_vector
(
31
downto
0
);
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_cyc_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
);
end
wb_reset
;
architecture
behaviour
of
wb_reset
is
constant
c_RST_REG
:
std_logic_vector
(
1
downto
0
)
:
=
"00"
;
signal
rst_reg
:
std_logic_vector
(
7
downto
0
);
signal
grst_net
:
std_logic_vector
(
20
downto
0
);
signal
grst_cpu
:
std_logic_vector
(
20
downto
0
);
signal
ack_int
:
std_logic
;
begin
process
(
clk_i
)
begin
if
(
rising_edge
(
clk_i
))
then
if
(
rst_n_i
=
'0'
)
then
ack_int
<=
'0'
;
rst_reg
<=
(
others
=>
'0'
);
else
if
(
wb_stb_i
=
'1'
and
wb_cyc_i
=
'1'
and
ack_int
=
'0'
)
then
if
(
wb_we_i
=
'1'
)
then
case
wb_addr_i
is
when
c_RST_REG
=>
rst_reg
<=
wb_data_i
(
7
downto
0
);
when
others
=>
end
case
;
end
if
;
ack_int
<=
'1'
;
else
ack_int
<=
'0'
;
end
if
;
end
if
;
end
if
;
end
process
;
wb_ack_o
<=
ack_int
;
process
(
clk_i
)
begin
if
(
rising_edge
(
clk_i
))
then
if
(
rst_n_i
=
'0'
)
then
grst_net
<=
(
others
=>
'1'
);
grst_cpu
<=
(
others
=>
'1'
);
else
grst_cpu
<=
grst_cpu
(
grst_cpu
'left
-1
downto
0
)
&
not
rst_reg
(
0
);
grst_net
<=
grst_net
(
grst_net
'left
-1
downto
0
)
&
not
rst_reg
(
1
);
end
if
;
end
if
;
end
process
;
rst_cpu_n_o
<=
grst_cpu
(
grst_cpu
'left
);
rst_net_n_o
<=
grst_net
(
grst_cpu
'left
);
end
behaviour
;
modules/wrc_core/wr_core.vhd
View file @
92c269b1
-------------------------------------------------------------------------------
-- Title : WhiteRabbit PTP Core
-- Title : WhiteRabbit PTP Core
-- Project : WhiteRabbit
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File : wr_core.vhd
-- File : wr_core.vhd
-- Author : Grzegorz Daniluk
-- Author : Grzegorz Daniluk
<grzegorz.daniluk@cern.ch>
-- Company : Elproma
-- Company :
CERN (BE-CO-HT),
Elproma
-- Created : 2011-02-02
-- Created : 2011-02-02
-- Last update: 2017-05-29
-- Last update: 2017-05-29
-- Platform : FPGA-generics
-- Platform : FPGA-generics
...
@@ -42,17 +43,7 @@
...
@@ -42,17 +43,7 @@
-- from http://www.gnu.org/licenses/lgpl-2.1.html
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-02 1.0 greg.d Created
-- 2011-10-25 2.0 greg.d Redesigned and wishbonized
-- 2012-03-05 3.0 wterpstra Added SDB descriptors
-------------------------------------------------------------------------------
-- Memory map:
-- Memory map:
-- Master interconnect:
-- 0x00000000: I/D Memory
-- 0x00000000: I/D Memory
-- 0x00020000: Peripheral interconnect
-- 0x00020000: Peripheral interconnect
-- +0x000: Minic
-- +0x000: Minic
...
@@ -63,6 +54,7 @@
...
@@ -63,6 +54,7 @@
-- +0x500: UART
-- +0x500: UART
-- +0x600: OneWire
-- +0x600: OneWire
-- +0x700: Auxillary space (Etherbone config, etc)
-- +0x700: Auxillary space (Etherbone config, etc)
-- +0x800: WRPC diagnostics registers
library
ieee
;
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
std_logic_1164
.
all
;
...
...
modules/wrc_core/wrc_periph.vhd
View file @
92c269b1
...
@@ -3,8 +3,8 @@
...
@@ -3,8 +3,8 @@
-- Project : WhiteRabbit
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File : wrc_periph.vhd
-- File : wrc_periph.vhd
-- Author : Grzegorz Daniluk
-- Author : Grzegorz Daniluk
<grzegorz.daniluk@cern.ch>
-- Company : Elproma
-- Company :
CERN (BE-CO-HT),
Elproma
-- Created : 2011-04-04
-- Created : 2011-04-04
-- Last update: 2017-04-25
-- Last update: 2017-04-25
-- Platform : FPGA-generics
-- Platform : FPGA-generics
...
@@ -14,12 +14,26 @@
...
@@ -14,12 +14,26 @@
-- WRC_PERIPH integrates WRC_SYSCON, UART/VUART, 1-Wire Master, WRPC_DIAGS
-- WRC_PERIPH integrates WRC_SYSCON, UART/VUART, 1-Wire Master, WRPC_DIAGS
--
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Grzegorz Daniluk
--
-------------------------------------------------------------------------------
-- Copyright (c) 2011, 2012 Elproma Elektronika
-- Revisions :
-- Copyright (c) 2012, 2017 CERN
-- Date Version Author Description
--
-- 2011-04-04 1.0 greg.d Created
-- This source file is free software; you can redistribute it
-- 2011-10-26 2.0 greg.d Redesigned
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library
ieee
;
library
ieee
;
...
...
modules/wrc_core/wrcore_pkg.vhd
View file @
92c269b1
-------------------------------------------------------------------------------
-- Title : WhiteRabbit PTP Core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wrcore_pkg.vhd
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT), Elproma
-- Created : 2011-05-11
-- Last update: 2017-05-29
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011, 2012 Elproma Elektronika
-- Copyright (c) 2012, 2017 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
std_logic_1164
.
all
;
...
...
modules/wrc_core/xwr_core.vhd
View file @
92c269b1
...
@@ -2,9 +2,9 @@
...
@@ -2,9 +2,9 @@
-- Title : WhiteRabbit PTP Core
-- Title : WhiteRabbit PTP Core
-- Project : WhiteRabbit
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File : wr_core.vhd
-- File :
x
wr_core.vhd
-- Author : Grzegorz Daniluk
-- Author : Grzegorz Daniluk
<grzegorz.daniluk@cern.ch>
-- Company : Elproma
-- Company :
CERN (BE-CO-HT),
Elproma
-- Created : 2011-02-02
-- Created : 2011-02-02
-- Last update: 2017-05-29
-- Last update: 2017-05-29
-- Platform : FPGA-generics
-- Platform : FPGA-generics
...
@@ -24,7 +24,7 @@
...
@@ -24,7 +24,7 @@
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- Copyright (c) 2011, 2012 Elproma Elektronika
-- Copyright (c) 2011, 2012 Elproma Elektronika
-- Copyright (c) 2012, 201
3
CERN
-- Copyright (c) 2012, 201
7
CERN
--
--
-- This source file is free software; you can redistribute it
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- and/or modify it under the terms of the GNU Lesser General
...
@@ -43,11 +43,18 @@
...
@@ -43,11 +43,18 @@
-- from http://www.gnu.org/licenses/lgpl-2.1.html
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Memory map:
-- Date Version Author Description
-- 0x00000000: I/D Memory
-- 2011-02-02 1.0 greg.d Created
-- 0x00020000: Peripheral interconnect
-- 2011-10-25 2.0 greg.d Redesigned and wishbonized
-- +0x000: Minic
-------------------------------------------------------------------------------
-- +0x100: Endpoint
-- +0x200: Softpll
-- +0x300: PPS gen
-- +0x400: Syscon
-- +0x500: UART
-- +0x600: OneWire
-- +0x700: Auxillary space (Etherbone config, etc)
-- +0x800: WRPC diagnostics registers
library
ieee
;
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
std_logic_1164
.
all
;
...
...
modules/wrc_core/xwr_syscon_wb.vhd
View file @
92c269b1
...
@@ -3,8 +3,8 @@
...
@@ -3,8 +3,8 @@
-- Project : WhiteRabbit
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File : xwr_syscon_wb.vhd
-- File : xwr_syscon_wb.vhd
-- Author : Grzegorz Daniluk
-- Author : Grzegorz Daniluk
<grzegorz.daniluk@cern.ch>
-- Company : Elproma
-- Company :
CERN(BE-CO-HT),
Elproma
-- Created : 2011-11-07
-- Created : 2011-11-07
-- Last update: 2017-04-20
-- Last update: 2017-04-20
-- Platform : FPGA-generics
-- Platform : FPGA-generics
...
@@ -15,11 +15,26 @@
...
@@ -15,11 +15,26 @@
-- can use pipelined or classic wishbone.
-- can use pipelined or classic wishbone.
--
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Grzegorz Daniluk
--
-------------------------------------------------------------------------------
-- Copyright (c) 2011-2012 Elproma Elektronika
-- Revisions :
-- Copyright (c) 2012-2017 CERN
-- Date Version Author Description
--
-- 2011-11-07 1.0 greg.d Created
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library
ieee
;
library
ieee
;
...
...
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