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White Rabbit core collection
Commit 91393b45 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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testbench/wr_endpoint: added packet filter init code

parent de74b82b
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Showing with 84 additions and 63 deletions
testbench/wr_endpoint/full_tb/endpoint_phy_wrapper.svh
View file @ 91393b45
......@@ -38,8 +38,8 @@ module endpoint_phy_wrapper
generate
if(g_phy_type == "TBI") begin
assign rx_clock = clk_rx_i;
assign tx_clock = clk_ref_i;
assign rx_clock = clk_ref_i;
assign tx_clock = clk_rx_i;
wr_tbi_phy U_Phy
......@@ -61,11 +61,11 @@ module endpoint_phy_wrapper
.serdes_rx_bitslide_o (grx_bitslide),
.tbi_refclk_i (clk_ref_new),
.tbi_rbclk_i (clk_ref_old),
.tbi_refclk_i (clk_ref_i),
.tbi_rbclk_i (clk_rx_i),
.tbi_td_o (n2o),
.tbi_rd_i (o2n),
.tbi_td_o (td_o),
.tbi_rd_i (rd_i),
.tbi_syncen_o (),
.tbi_loopen_o (),
.tbi_prbsen_o (),
......@@ -112,7 +112,7 @@ module endpoint_phy_wrapper
.g_with_rx_buffer(0),
.g_with_timestamper (1),
.g_with_dmtd (0),
.g_with_dpi_classifier (0),
.g_with_dpi_classifier (1),
.g_with_vlans (0),
.g_with_rtu (0)
) DUT (
......@@ -147,6 +147,7 @@ module endpoint_phy_wrapper
.src_we_o (snk.we),
.src_stall_i (snk.stall),
.src_ack_i (snk.ack),
.src_err_i(1'b0),
.snk_dat_i (src.dat_o[15:0]),
.snk_adr_i (src.adr[1:0]),
......@@ -179,7 +180,7 @@ module endpoint_phy_wrapper
.wb_stb_i (sys.stb),
.wb_we_i (sys.we),
.wb_sel_i(sys.sel),
.wb_adr_i(sys.adr[5:0]),
.wb_adr_i(sys.adr[7:0]),
.wb_dat_i(sys.dat_o),
.wb_dat_o(sys.dat_i),
.wb_ack_o (sys.ack)
......
testbench/wr_endpoint/full_tb/main.sv
View file @ 91393b45
......@@ -19,6 +19,7 @@
class CSimDrv_WR_Endpoint;
protected CBusAccessor m_acc;
......@@ -51,7 +52,32 @@ class CSimDrv_WR_Endpoint;
task pfilter_enable(int enable);
m_acc.write(m_base + `ADDR_EP_PFCR0, enable ? `EP_PFCR0_ENABLE: 0);
endtask
endtask // pfilter_enable
task automatic mdio_read(int base, int addr, output int val);
reg[31:0] rval;
m_acc.write(base+`ADDR_EP_MDIO_CR, (addr>>2) << 16);
while(1)begin
m_acc.read(base+`ADDR_EP_MDIO_SR, rval);
if(rval[31]) begin
val = rval[15:0];
return;
end
end
endtask // mdio_read
task automatic mdio_write(int base, int addr,int val);
reg[31:0] rval;
m_acc.write(base+`ADDR_EP_MDIO_CR, (addr>>2) << 16 | `EP_MDIO_CR_RW);
while(1)begin
m_acc.read(base+`ADDR_EP_MDIO_SR, rval);
if(rval[31])
return;
end
endtask // automatic
endclass // CSimDrv_WR_Endpoint
......@@ -113,22 +139,31 @@ module main;
);
wire rxn,rxp,txn,txp;
wire [9:0] td;
wire [9:0] rd;
old_endpoint_test_wrapper
#(
.g_phy_type("GTP"))
.g_phy_type("TBI"))
U_oldep_wrap
(
.clk_sys_i(clk_sys),
.clk_ref_i(clk_ref_old),
.clk_rx_i(clk_ref_new),
.rst_n_i(rst_n),
.td_o(td),
.rd_i(rd)
/* -----\/----- EXCLUDED -----\/-----
.rxp_i(rxp),
.rxn_i(rxn),
.txp_o(txp),
.txn_o(txn)
-----/\----- EXCLUDED -----/\----- */
);
reg clk_ref_gtx = 1;
......@@ -137,22 +172,28 @@ module main;
endpoint_phy_wrapper
#(
.g_phy_type("GTX"))
.g_phy_type("TBI"))
U_Wrapped_EP
(
.clk_sys_i(clk_sys),
.clk_ref_i(clk_ref_new),
.clk_ref_i(clk_ref_new),
.clk_rx_i(clk_ref_new),
.rst_n_i(rst_n),
.snk (U_wrf_sink.slave),
.src(U_wrf_source.master),
.sys(U_sys_bus_master.master),
.td_o(rd),
.rd_i(td)
/* -----\/----- EXCLUDED -----\/-----
.txn_o(rxn),
.txp_o(rxp),
.rxn_i(txn),
.rxp_i(txp)
-----/\----- EXCLUDED -----/\----- */
);
......@@ -204,12 +245,13 @@ module main;
tmpl = new;
tmpl.src = '{1,2,3,4,5,6};
tmpl.dst = '{10,11,12,13,14,15};
tmpl.dst = '{'h00, 'h50, 'hca, 'hfe, 'hba, 'hbe};
tmpl.has_smac = 1;
tmpl.is_q = is_q;
tmpl.vid = 100;
gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD | EthPacketGenerator::ETHERTYPE/* | EthPacketGenerator::TX_OOB*/) ;
tmpl.ethertype = 'h88f7;
//
gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD /* | EthPacketGenerator::TX_OOB*/) ;
gen.set_template(tmpl);
gen.set_size(64,1500);
......@@ -245,23 +287,30 @@ module main;
task init_pfilter(CSimDrv_WR_Endpoint ep_drv);
PFilterMicrocode mc = new;
mc.cmp(0, 'h0a0b, 'hffff, PFilterMicrocode::MOV, 1);
mc.cmp(1, 'h0c0a, 'hffff, PFilterMicrocode::AND, 1);
mc.cmp(2, 'h0e0f, 'hffff, PFilterMicrocode::AND, 1);
mc.logic2(2, 1, PFilterMicrocode::MOV, 0);
mc.cmp(3, 'h0102, 'hffff, PFilterMicrocode::MOV, 1);
mc.cmp(4, 'h030a, 'hffff, PFilterMicrocode::AND, 1);
mc.cmp(5, 'h0506, 'hffff, PFilterMicrocode::AND, 1);
mc.logic2(3, 1, PFilterMicrocode::MOV, 0);
mc.cmp(6,'h86ba, 'hffff, PFilterMicrocode::MOV, 4);
mc.logic3(5, 2, PFilterMicrocode::AND, 3, PFilterMicrocode::OR, 4);
mc.cmp(0, 'hffff, 'hffff, PFilterMicrocode::MOV, 1);
mc.cmp(1, 'hffff, 'hffff, PFilterMicrocode::AND, 1);
mc.cmp(2, 'hffff, 'hffff, PFilterMicrocode::AND, 1);
mc.cmp(0, 'h011b, 'hffff, PFilterMicrocode::MOV, 2);
mc.cmp(1, 'h1900, 'hffff, PFilterMicrocode::AND, 2);
mc.cmp(2, 'h0000, 'hffff, PFilterMicrocode::AND, 2);
mc.cmp(0, 'h0050, 'hffff, PFilterMicrocode::MOV, 3);
mc.cmp(1, 'hcafe, 'hffff, PFilterMicrocode::AND, 3);
mc.cmp(2, 'hbabe, 'hffff, PFilterMicrocode::AND, 3);
mc.cmp(6, 'ha0a0, 'hffff, PFilterMicrocode::MOV, 4);
mc.cmp(6, 'h88f7, 'hffff, PFilterMicrocode::MOV, 5);
mc.logic3(7, 3, PFilterMicrocode::AND, 4, PFilterMicrocode::OR, 5);
mc.logic2(23, 7, PFilterMicrocode::NOT, 0);
mc.logic2(31, 3, PFilterMicrocode::AND, 4);
mc.logic2(24, 5, PFilterMicrocode::MOV, 0);
ep_drv.pfilter_load_microcode(mc.assemble());
ep_drv.pfilter_enable(1);
endtask // init_pfilter
initial begin
CWishboneAccessor sys_bus;
WBPacketSource src = new(U_wrf_source.get_accessor());
......@@ -326,8 +375,10 @@ module main;
begin
$display("RX Iter %d", i);
tx_test(5, 0, 0, o_src, sink);
/* -----\/----- EXCLUDED -----\/-----
$display("TX Iter %d", i);
tx_test(5, 0, 0, src, o_sink);
-----/\----- EXCLUDED -----/\----- */
end
end // initial begin
......
testbench/wr_endpoint/full_tb/wave.do
View file @ 91393b45
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/clk_sys
add wave -noupdate /main/clk_ref
add wave -noupdate /main/clk_tdc
add wave -noupdate /main/rst_n
add wave -noupdate /main/trig_a
add wave -noupdate /main/trig_cal
add wave -noupdate /main/acam_wr_n
add wave -noupdate /main/acam_cs_n
add wave -noupdate /main/acam_rd_n
add wave -noupdate /main/acam_oe_n
add wave -noupdate /main/acam_adr
add wave -noupdate /main/acam_data
add wave -noupdate /main/tdc_d_o
add wave -noupdate /main/tdc_d_oe
add wave -noupdate /main/acam_start_dis
add wave -noupdate /main/acam_stop_dis
add wave -noupdate /main/acam_alutrigger
add wave -noupdate /main/trig_a_n_delayed
add wave -noupdate /main/tdc_start_delayed
add wave -noupdate /main/wr_utc
add wave -noupdate /main/wr_coarse
add wave -noupdate /main/wr_time_valid
add wave -noupdate /main/tdc_start_div
add wave -noupdate /main/tdc_start
add wave -noupdate /main/wr_time_valid_d0
add wave -noupdate /main/acam_ef1
add wave -noupdate /main/delay_len
add wave -noupdate /main/delay_pulse
add wave -noupdate /main/delay_val
add wave -noupdate /main/d_out
add wave -noupdate /main/spi_loop
add wave -noupdate /main/c_coarse_range
add wave -noupdate /main/fd_drv
add wave -noupdate /main/wb
add wave -noupdate /main/prev
add wave -noupdate /main/U_Wrapped_EP/DUT/U_Rx_Path/dreq_pipe
add wave -noupdate /main/U_Wrapped_EP/DUT/U_Rx_Path/fab_pipe
add wave -noupdate /main/U_Wrapped_EP/DUT/U_Rx_Path/src_wb_o
add wave -noupdate /main/U_Wrapped_EP/DUT/U_Rx_Path/src_wb_i
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {20442364860 fs} 0}
WaveRestoreCursors {{Cursor 1} {199349192100 fs} 0}
configure wave -namecolwidth 413
configure wave -valuecolwidth 100
configure wave -justifyvalue left
......@@ -51,4 +20,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 fs} {6754054050 fs}
WaveRestoreZoom {0 fs} {262500 ns}
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