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White Rabbit core collection
Commit de74b82b authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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modules/wrc_lm32: removed legacy CPU core (now uses wr-cores)

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Manifest.py
View file @ de74b82b
......@@ -2,11 +2,11 @@ fetchto = "ip_cores"
modules = {"local" :
[ "platform/xilinx/wr_gtp_phy",
"modules/fabric",
"modules/wr_tbi_phy",
"modules/timing",
"modules/wr_mini_nic",
"modules/wr_softpll",
"modules/wrc_lm32",
"modules/wr_endpoint",
"modules/wr_pps_gen",
"modules/wrc_core" ],
......
modules/wrc_lm32/Manifest.py deleted 100644 → 0
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files = [ "wrc_lm32.vhd",
"lm32_cpu.v",
"lm32_addsub.v",
"lm32_top.v",
"lm32_instruction_unit.v",
"lm32_decoder.v",
"lm32_load_store_unit.v",
"lm32_adder.v",
"lm32_logic_op.v",
"lm32_shifter.v",
"lm32_multiplier.v",
"lm32_interrupt.v",
"lm32_dp_ram.v",
"lm32_debug.v",
"lm32_jtag.v",
"jtag_wb.v"
];
\ No newline at end of file
modules/wrc_lm32/jtag_cores.v deleted 100644 → 0
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// Modified by GSI to use simple positive edge clocking and the JTAG capture state
`include "lm32_include.v"
module jtag_cores (
input [7:0] reg_d,
input [2:0] reg_addr_d,
output reg_update,
output [7:0] reg_q,
output [2:0] reg_addr_q,
output jtck,
output jrstn
);
wire tck;
wire tdi;
wire tdo;
wire capture;
wire shift;
wire update;
wire e1dr;
wire reset;
jtag_tap jtag_tap (
.tck(tck),
.tdi(tdi),
.tdo(tdo),
.capture(capture),
.shift(shift),
.e1dr(e1dr),
.update(update),
.reset(reset)
);
reg [10:0] jtag_shift;
reg [10:0] jtag_latched;
always @(posedge tck)
begin
if(reset)
jtag_shift <= 11'b0;
else begin
if (shift)
jtag_shift <= {tdi, jtag_shift[10:1]};
else if (capture)
jtag_shift <= {reg_d, reg_addr_d};
end
end
assign tdo = jtag_shift[0];
always @(posedge tck)
begin
if(reset)
jtag_latched <= 11'b0;
else begin
if (e1dr)
jtag_latched <= jtag_shift;
end
end
assign reg_update = update;
assign reg_q = jtag_latched[10:3];
assign reg_addr_q = jtag_latched[2:0];
assign jtck = tck;
assign jrstn = ~reset;
endmodule
modules/wrc_lm32/jtag_wb.v deleted 100644 → 0
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/* Added by GSI to support debug over wishbone */
`define ACK_DELAY 8 /* Give the JTAG core time to latch after a write */
`include "lm32_include.v"
module jtag_wb (
clk_i,
DAT_I,
ADR_I,
CYC_I,
SEL_I,
STB_I,
WE_I,
reg_d,
reg_addr_d,
ACK_O,
STALL_O,
DAT_O,
reg_update,
reg_q,
reg_addr_q,
jtck,
jrstn
);
input clk_i;
input [`LM32_WORD_RNG] DAT_I;
input [`LM32_WORD_RNG] ADR_I;
input CYC_I;
input [`LM32_BYTE_SELECT_RNG] SEL_I;
input STB_I;
input WE_I;
input [7:0] reg_d;
input [2:0] reg_addr_d;
output ACK_O;
output STALL_O;
output [`LM32_WORD_RNG] DAT_O;
output reg_update;
output [7:0] reg_q;
output [2:0] reg_addr_q;
output jtck;
output jrstn;
reg [7:0] reg_q;
reg [2:0] reg_addr_q;
reg [`ACK_DELAY-1:0] ack_shift;
assign reg_update = (CYC_I == `TRUE) &&
(STB_I == `TRUE) &&
(WE_I == `TRUE);
assign DAT_O[31:11] = 21'h0;
assign DAT_O[10:3] = reg_d;
assign DAT_O[2:0] = reg_addr_d;
assign jtck = clk_i;
assign jrstn = 1;
assign ACK_O = ack_shift[0];
assign STALL_O = |ack_shift[`ACK_DELAY-1:1];
always @(posedge clk_i)
begin
ack_shift <=
{CYC_I == `TRUE && STB_I == `TRUE && STALL_O == `FALSE,
ack_shift[`ACK_DELAY-1:1]};
if (reg_update == `TRUE)
begin
reg_q <= DAT_I[10:3];
reg_addr_q <= DAT_I[2:0];
end
end
endmodule
modules/wrc_lm32/lm32_adder.v deleted 100644 → 0
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// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court 408-826-6000 (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email: techsupport@latticesemi.com
// ============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_adder.v
// Title : Integer adder / subtractor with comparison flag generation
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_adder (
// ----- Inputs -------
adder_op_x,
adder_op_x_n,
operand_0_x,
operand_1_x,
// ----- Outputs -------
adder_result_x,
adder_carry_n_x,
adder_overflow_x
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input adder_op_x; // Operating to perform, 0 for addition, 1 for subtraction
input adder_op_x_n; // Inverted version of adder_op_x
input [`LM32_WORD_RNG] operand_0_x; // Operand to add, or subtract from
input [`LM32_WORD_RNG] operand_1_x; // Opearnd to add, or subtract by
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output [`LM32_WORD_RNG] adder_result_x; // Result of addition or subtraction
wire [`LM32_WORD_RNG] adder_result_x;
output adder_carry_n_x; // Inverted carry
wire adder_carry_n_x;
output adder_overflow_x; // Indicates if overflow occured, only valid for subtractions
reg adder_overflow_x;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
wire a_sign; // Sign (i.e. positive or negative) of operand 0
wire b_sign; // Sign of operand 1
wire result_sign; // Sign of result
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
lm32_addsub addsub (
// ----- Inputs -----
.DataA (operand_0_x),
.DataB (operand_1_x),
.Cin (adder_op_x),
.Add_Sub (adder_op_x_n),
// ----- Ouputs -----
.Result (adder_result_x),
.Cout (adder_carry_n_x)
);
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
// Extract signs of operands and result
assign a_sign = operand_0_x[`LM32_WORD_WIDTH-1];
assign b_sign = operand_1_x[`LM32_WORD_WIDTH-1];
assign result_sign = adder_result_x[`LM32_WORD_WIDTH-1];
// Determine whether an overflow occured when performing a subtraction
always @(*)
begin
// +ve - -ve = -ve -> overflow
// -ve - +ve = +ve -> overflow
if ( (!a_sign & b_sign & result_sign)
|| (a_sign & !b_sign & !result_sign)
)
adder_overflow_x = `TRUE;
else
adder_overflow_x = `FALSE;
end
endmodule
modules/wrc_lm32/lm32_addsub.v deleted 100644 → 0
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// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court 408-826-6000 (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email: techsupport@latticesemi.com
// =============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_addsub.v
// Title : PMI adder/subtractor.
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_addsub (
// ----- Inputs -------
DataA,
DataB,
Cin,
Add_Sub,
// ----- Outputs -------
Result,
Cout
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input [31:0] DataA;
input [31:0] DataB;
input Cin;
input Add_Sub;
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output [31:0] Result;
wire [31:0] Result;
output Cout;
wire Cout;
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
// Modified for Milkymist: removed non-portable instantiated block
wire [32:0] tmp_addResult = DataA + DataB + Cin;
wire [32:0] tmp_subResult = DataA - DataB - !Cin;
assign Result = (Add_Sub == 1) ? tmp_addResult[31:0] : tmp_subResult[31:0];
assign Cout = (Add_Sub == 1) ? tmp_addResult[32] : !tmp_subResult[32];
endmodule
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modules/wrc_lm32/lm32_dp_ram.v deleted 100644 → 0
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module lm32_dp_ram(
clk_i,
rst_i,
we_i,
waddr_i,
wdata_i,
raddr_i,
rdata_o);
parameter addr_width = 32;
parameter addr_depth = 1024;
parameter data_width = 8;
input clk_i;
input rst_i;
input we_i;
input [addr_width-1:0] waddr_i;
input [data_width-1:0] wdata_i;
input [addr_width-1:0] raddr_i;
output [data_width-1:0] rdata_o;
reg [data_width-1:0] ram[addr_depth-1:0];
reg [addr_width-1:0] raddr_r;
assign rdata_o = ram[raddr_r];
integer i;
initial begin
for (i=0;i<(1<<addr_depth)-1;i=i+1)
ram[i] = 0;
end
always @ (posedge clk_i)
begin
if (we_i)
ram[waddr_i] <= wdata_i;
raddr_r <= raddr_i;
end
endmodule
modules/wrc_lm32/lm32_functions.v deleted 100644 → 0
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// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court 408-826-6000 (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email: techsupport@latticesemi.com
// =============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_functions.v
// Title : Common functions
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.5
// : Added function to generate log-of-two that rounds-up to
// : power-of-two
// =============================================================================
function integer clogb2;
input [31:0] value;
begin
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
value = value >> 1;
end
endfunction
function integer clogb2_v1;
input [31:0] value;
reg [31:0] i;
reg [31:0] temp;
begin
temp = 0;
i = 0;
for (i = 0; temp < value; i = i + 1)
temp = 1<<i;
clogb2_v1 = i-1;
end
endfunction
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_package.all;
package lm32_package is
component lm32_vhdl is
port(
clk : in std_logic;
rst : in std_logic;
interrupt : in std_logic_vector(31 downto 0);
-- Data bus wishbone master:
data_o : out wishbone_master_out;
data_i : in wishbone_master_in;
-- Instruction bus wishbone master:
inst_o : out wishbone_master_out;
inst_i : in wishbone_master_in);
end component;
end;
modules/wrc_lm32/lm32_ram.v deleted 100644 → 0
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modules/wrc_lm32/system_conf.v deleted 100644 → 0
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`ifdef LM32_CONFIG_V
`else
`define LM32_CONFIG_V
//
// Common configuration options
//
`define CFG_EBA_RESET 32'h00000000
//`define CFG_DEBA_RESET 32'h10000000
`define CFG_DEBA_RESET 32'h00000000
`define CFG_PL_MULTIPLY_ENABLED
`define CFG_PL_BARREL_SHIFT_ENABLED
//`define CFG_SIGN_EXTEND_ENABLED
//`define CFG_MC_DIVIDE_ENABLED
// bi and calli -> 2 cycles
//`define CFG_FAST_UNCONDITIONAL_BRANCH
// 2k memory cheaper than 1k registers+logic
`define CFG_EBR_POSEDGE_REGISTER_FILE
//`define CFG_ICACHE_ENABLED
//`define CFG_ICACHE_ASSOCIATIVITY 1
//`define CFG_ICACHE_SETS 256
//`define CFG_ICACHE_BYTES_PER_LINE 16
//`define CFG_ICACHE_BASE_ADDRESS 32'h0
//`define CFG_ICACHE_LIMIT 32'h7fffffff
//`define CFG_DCACHE_ENABLED
//`define CFG_DCACHE_ASSOCIATIVITY 1
//`define CFG_DCACHE_SETS 256
//`define CFG_DCACHE_BYTES_PER_LINE 16
//`define CFG_DCACHE_BASE_ADDRESS 32'h0
//`define CFG_DCACHE_LIMIT 32'h7fffffff
// Enable Debugging
`define CFG_TRACE_ENABLED
`define CFG_JTAG_ENABLED
`define CFG_JTAG_UART_ENABLED
`define CFG_DEBUG_ENABLED
`define CFG_HW_DEBUG_ENABLED
`define CFG_BREAKPOINTS 32'h4
`define CFG_WATCHPOINTS 32'h4
`define CFG_JWB_ENABLED
`define CFG_INTERRUPTS_ENABLED
//`define CFG_BUS_ERRORS_ENABLED
`endif
modules/wrc_lm32/wrc_lm32.vhd deleted 100644 → 0
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