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White Rabbit core collection
Commit 8feb29dc authored by Tristan Gingold's avatar Tristan Gingold
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wrc_core: remove unused led_green and led_red

parent 3c5cf0df
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modules/wrc_core/wr_core.vhd
View file @ 8feb29dc
...@@ -897,8 +897,6 @@ begin ...@@ -897,8 +897,6 @@ begin
rst_net_n_o => rst_net_n, rst_net_n_o => rst_net_n,
rst_wrc_n_o => rst_wrc_n, rst_wrc_n_o => rst_wrc_n,
led_red_o => open, --led_red_o,
led_green_o => open, --led_green_o,
scl_o => scl_o, scl_o => scl_o,
scl_i => scl_i, scl_i => scl_i,
sda_o => sda_o, sda_o => sda_o,
......
modules/wrc_core/wrc_periph.vhd
View file @ 8feb29dc
...@@ -6,7 +6,6 @@ ...@@ -6,7 +6,6 @@
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch> -- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT) -- Company : CERN (BE-CO-HT)
-- Created : 2011-04-04 -- Created : 2011-04-04
-- Last update: 2023-04-26
-- Platform : FPGA-generics -- Platform : FPGA-generics
-- Standard : VHDL -- Standard : VHDL
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -70,8 +69,6 @@ entity wrc_periph is ...@@ -70,8 +69,6 @@ entity wrc_periph is
rst_net_n_o : out std_logic; rst_net_n_o : out std_logic;
rst_wrc_n_o : out std_logic; rst_wrc_n_o : out std_logic;
led_red_o : out std_logic;
led_green_o : out std_logic;
scl_o : out std_logic; scl_o : out std_logic;
scl_i : in std_logic; scl_i : in std_logic;
sda_o : out std_logic; sda_o : out std_logic;
...@@ -185,26 +182,6 @@ begin ...@@ -185,26 +182,6 @@ begin
end if; end if;
end process; end process;
-------------------------------------
-- LEDs
-------------------------------------
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(sysc_regs_o.gpsr_led_link_o = '1') then
led_red_o <= '1';
elsif(sysc_regs_o.gpcr_led_link_o = '1') then
led_red_o <= '0';
end if;
if(sysc_regs_o.gpsr_led_stat_o = '1') then
led_green_o <= '1';
elsif(sysc_regs_o.gpcr_led_stat_o = '1') then
led_green_o <= '0';
end if;
end if;
end process;
------------------------------------- -------------------------------------
-- buttons -- buttons
------------------------------------- -------------------------------------
......
modules/wrc_core/wrcore_pkg.vhd
View file @ 8feb29dc
...@@ -6,7 +6,6 @@ ...@@ -6,7 +6,6 @@
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch> -- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT) -- Company : CERN (BE-CO-HT)
-- Created : 2011-05-11 -- Created : 2011-05-11
-- Last update: 2023-05-05
-- Platform : FPGA-generics -- Platform : FPGA-generics
-- Standard : VHDL -- Standard : VHDL
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -297,8 +296,6 @@ package wrcore_pkg is ...@@ -297,8 +296,6 @@ package wrcore_pkg is
rst_n_i : in std_logic; rst_n_i : in std_logic;
rst_net_n_o : out std_logic; rst_net_n_o : out std_logic;
rst_wrc_n_o : out std_logic; rst_wrc_n_o : out std_logic;
led_red_o : out std_logic;
led_green_o : out std_logic;
scl_o : out std_logic; scl_o : out std_logic;
scl_i : in std_logic; scl_i : in std_logic;
sda_o : out std_logic; sda_o : out std_logic;
......
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