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White Rabbit core collection
Commit 8bc0d374 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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Merge branch 'abscal' into proposed_master

parents a595a117 099e58a1
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board/common/wr_board_pkg.vhd
View file @ 8bc0d374
...@@ -152,6 +152,8 @@ package wr_board_pkg is ...@@ -152,6 +152,8 @@ package wr_board_pkg is
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0); tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
timestamps_o : out t_txtsu_timestamp; timestamps_o : out t_txtsu_timestamp;
timestamps_ack_i : in std_logic := '1'; timestamps_ack_i : in std_logic := '1';
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
fc_tx_pause_req_i : in std_logic := '0'; fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000"; fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic; fc_tx_pause_ready_o : out std_logic;
......
board/common/xwrc_board_common.vhd
View file @ 8bc0d374
...@@ -216,6 +216,12 @@ entity xwrc_board_common is ...@@ -216,6 +216,12 @@ entity xwrc_board_common is
timestamps_o : out t_txtsu_timestamp; timestamps_o : out t_txtsu_timestamp;
timestamps_ack_i : in std_logic := '1'; timestamps_ack_i : in std_logic := '1';
-----------------------------------------
-- Timestamp helper signals, used for Absolute Calibration
-----------------------------------------
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
-- Pause Frame Control -- Pause Frame Control
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
...@@ -402,6 +408,8 @@ begin -- architecture struct ...@@ -402,6 +408,8 @@ begin -- architecture struct
wrf_snk_i => wrf_snk_in, wrf_snk_i => wrf_snk_in,
timestamps_o => timestamps_o, timestamps_o => timestamps_o,
timestamps_ack_i => timestamps_ack_i, timestamps_ack_i => timestamps_ack_i,
abscal_txts_o => abscal_txts_o,
abscal_rxts_o => abscal_rxts_o,
fc_tx_pause_req_i => fc_tx_pause_req_i, fc_tx_pause_req_i => fc_tx_pause_req_i,
fc_tx_pause_delay_i => fc_tx_pause_delay_i, fc_tx_pause_delay_i => fc_tx_pause_delay_i,
fc_tx_pause_ready_o => fc_tx_pause_ready_o, fc_tx_pause_ready_o => fc_tx_pause_ready_o,
......
board/spec/wr_spec_pkg.vhd
View file @ 8bc0d374
...@@ -97,6 +97,8 @@ package wr_spec_pkg is ...@@ -97,6 +97,8 @@ package wr_spec_pkg is
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0); tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
timestamps_o : out t_txtsu_timestamp; timestamps_o : out t_txtsu_timestamp;
timestamps_ack_i : in std_logic := '1'; timestamps_ack_i : in std_logic := '1';
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
fc_tx_pause_req_i : in std_logic := '0'; fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000"; fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic; fc_tx_pause_ready_o : out std_logic;
......
board/spec/wrc_board_spec.vhd
View file @ 8bc0d374
...@@ -260,6 +260,12 @@ entity wrc_board_spec is ...@@ -260,6 +260,12 @@ entity wrc_board_spec is
tstamps_incorrect_o : out std_logic; tstamps_incorrect_o : out std_logic;
tstamps_ack_i : in std_logic := '1'; tstamps_ack_i : in std_logic := '1';
-----------------------------------------
-- Timestamp helper signals, used for Absolute Calibration
-----------------------------------------
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
-- Pause Frame Control -- Pause Frame Control
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
...@@ -485,6 +491,8 @@ begin -- architecture struct ...@@ -485,6 +491,8 @@ begin -- architecture struct
tm_clk_aux_locked_o => tm_clk_aux_locked_o, tm_clk_aux_locked_o => tm_clk_aux_locked_o,
timestamps_o => timestamps_out, timestamps_o => timestamps_out,
timestamps_ack_i => tstamps_ack_i, timestamps_ack_i => tstamps_ack_i,
abscal_txts_o => abscal_txts_o,
abscal_rxts_o => abscal_rxts_o,
fc_tx_pause_req_i => fc_tx_pause_req_i, fc_tx_pause_req_i => fc_tx_pause_req_i,
fc_tx_pause_delay_i => fc_tx_pause_delay_i, fc_tx_pause_delay_i => fc_tx_pause_delay_i,
fc_tx_pause_ready_o => fc_tx_pause_ready_o, fc_tx_pause_ready_o => fc_tx_pause_ready_o,
......
board/spec/xwrc_board_spec.vhd
View file @ 8bc0d374
...@@ -216,6 +216,12 @@ entity xwrc_board_spec is ...@@ -216,6 +216,12 @@ entity xwrc_board_spec is
timestamps_o : out t_txtsu_timestamp; timestamps_o : out t_txtsu_timestamp;
timestamps_ack_i : in std_logic := '1'; timestamps_ack_i : in std_logic := '1';
-----------------------------------------
-- Timestamp helper signals, used for Absolute Calibration
-----------------------------------------
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
-- Pause Frame Control -- Pause Frame Control
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
...@@ -496,6 +502,8 @@ begin -- architecture struct ...@@ -496,6 +502,8 @@ begin -- architecture struct
tm_clk_aux_locked_o => tm_clk_aux_locked_o, tm_clk_aux_locked_o => tm_clk_aux_locked_o,
timestamps_o => timestamps_o, timestamps_o => timestamps_o,
timestamps_ack_i => timestamps_ack_i, timestamps_ack_i => timestamps_ack_i,
abscal_txts_o => abscal_txts_o,
abscal_rxts_o => abscal_rxts_o,
fc_tx_pause_req_i => fc_tx_pause_req_i, fc_tx_pause_req_i => fc_tx_pause_req_i,
fc_tx_pause_delay_i => fc_tx_pause_delay_i, fc_tx_pause_delay_i => fc_tx_pause_delay_i,
fc_tx_pause_ready_o => fc_tx_pause_ready_o, fc_tx_pause_ready_o => fc_tx_pause_ready_o,
......
modules/wr_endpoint/endpoint_pkg.vhd
View file @ 8bc0d374
...@@ -265,6 +265,8 @@ package endpoint_pkg is ...@@ -265,6 +265,8 @@ package endpoint_pkg is
inject_packet_sel_i : in std_logic_vector(2 downto 0) := "000"; inject_packet_sel_i : in std_logic_vector(2 downto 0) := "000";
inject_user_value_i : in std_logic_vector(15 downto 0) := x"0000"; inject_user_value_i : in std_logic_vector(15 downto 0) := x"0000";
rmon_events_o : out std_logic_vector(c_epevents_sz-1 downto 0); rmon_events_o : out std_logic_vector(c_epevents_sz-1 downto 0);
txts_o : out std_logic; -- 2013-Nov-28 peterj added for debugging/calibration
rxts_o : out std_logic; -- 2013-Nov-28 peterj added for debugging/calibration
led_link_o : out std_logic; led_link_o : out std_logic;
led_act_o : out std_logic; led_act_o : out std_logic;
link_kill_i : in std_logic := '0'; link_kill_i : in std_logic := '0';
...@@ -392,6 +394,8 @@ package endpoint_pkg is ...@@ -392,6 +394,8 @@ package endpoint_pkg is
inject_packet_sel_i : in std_logic_vector(2 downto 0) := "000"; inject_packet_sel_i : in std_logic_vector(2 downto 0) := "000";
inject_user_value_i : in std_logic_vector(15 downto 0) := x"0000"; inject_user_value_i : in std_logic_vector(15 downto 0) := x"0000";
rmon_events_o : out std_logic_vector(c_epevents_sz-1 downto 0); rmon_events_o : out std_logic_vector(c_epevents_sz-1 downto 0);
txts_o : out std_logic; -- 2013-Nov-28 peterj added for debugging/calibration
rxts_o : out std_logic; -- 2013-Nov-28 peterj added for debugging/calibration
led_link_o : out std_logic; led_link_o : out std_logic;
led_act_o : out std_logic; led_act_o : out std_logic;
link_kill_i : in std_logic := '0'; link_kill_i : in std_logic := '0';
......
modules/wr_endpoint/endpoint_private_pkg.vhd
View file @ 8bc0d374
...@@ -423,6 +423,8 @@ package endpoint_private_pkg is ...@@ -423,6 +423,8 @@ package endpoint_private_pkg is
txts_timestamp_o : out std_logic_vector(31 downto 0); txts_timestamp_o : out std_logic_vector(31 downto 0);
txts_timestamp_stb_o : out std_logic; txts_timestamp_stb_o : out std_logic;
txts_timestamp_valid_o : out std_logic; txts_timestamp_valid_o : out std_logic;
txts_o : out std_logic; -- 2013-Nov-28 peterj added for debugging/calibration
rxts_o : out std_logic; -- 2013-Nov-28 peterj added for debugging/calibration
regs_i : in t_ep_out_registers; regs_i : in t_ep_out_registers;
regs_o : out t_ep_in_registers); regs_o : out t_ep_in_registers);
end component; end component;
......
modules/wr_endpoint/ep_timestamping_unit.vhd
View file @ 8bc0d374
...@@ -101,6 +101,8 @@ entity ep_timestamping_unit is ...@@ -101,6 +101,8 @@ entity ep_timestamping_unit is
-- TX timestamp valid (to TXTSU/Framer) -- TX timestamp valid (to TXTSU/Framer)
txts_timestamp_valid_o : out std_logic; txts_timestamp_valid_o : out std_logic;
txts_o : out std_logic; -- 2013-Nov-28 peterj added for debugging/calibration
rxts_o : out std_logic; -- 2013-Nov-28 peterj added for debugging/calibration
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Wishbone regs -- Wishbone regs
...@@ -363,6 +365,9 @@ begin -- syn ...@@ -363,6 +365,9 @@ begin -- syn
npulse_o => rx_ts_done, npulse_o => rx_ts_done,
ppulse_o => open); ppulse_o => open);
txts_o <= tx_ts_done; -- 2013-Nov-28 peterj added for debugging/calibration
rxts_o <= rx_ts_done; -- 2013-Nov-28 peterj added for debugging/calibration
p_output_rx_ts : process (clk_rx_i) p_output_rx_ts : process (clk_rx_i)
begin begin
if rising_edge(clk_rx_i) then if rising_edge(clk_rx_i) then
......
modules/wr_endpoint/wr_endpoint.vhd
View file @ 8bc0d374
...@@ -286,6 +286,9 @@ entity wr_endpoint is ...@@ -286,6 +286,9 @@ entity wr_endpoint is
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
rmon_events_o : out std_logic_vector(c_epevents_sz-1 downto 0); rmon_events_o : out std_logic_vector(c_epevents_sz-1 downto 0);
txts_o : out std_logic; -- 2013-Nov-28 peterj added for debugging/calibration
rxts_o : out std_logic; -- 2013-Nov-28 peterj added for debugging/calibration
led_link_o : out std_logic; led_link_o : out std_logic;
led_act_o : out std_logic; led_act_o : out std_logic;
...@@ -710,6 +713,9 @@ begin ...@@ -710,6 +713,9 @@ begin
txts_timestamp_o => txts_timestamp_value, txts_timestamp_o => txts_timestamp_value,
txts_timestamp_valid_o => txts_timestamp_valid, txts_timestamp_valid_o => txts_timestamp_valid,
txts_o => txts_o, -- 2013-Nov-28 peterj added for debugging/calibration
rxts_o => rxts_o, -- 2013-Nov-28 peterj added for debugging/calibration
regs_i => regs_fromwb, regs_i => regs_fromwb,
regs_o => regs_towb_tsu); regs_o => regs_towb_tsu);
......
modules/wr_endpoint/xwr_endpoint.vhd
View file @ 8bc0d374
...@@ -260,6 +260,9 @@ entity xwr_endpoint is ...@@ -260,6 +260,9 @@ entity xwr_endpoint is
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
rmon_events_o : out std_logic_vector(c_epevents_sz-1 downto 0); rmon_events_o : out std_logic_vector(c_epevents_sz-1 downto 0);
txts_o : out std_logic; -- 2013-Nov-28 peterj added for debugging/calibration
rxts_o : out std_logic; -- 2013-Nov-28 peterj added for debugging/calibration
led_link_o : out std_logic; led_link_o : out std_logic;
led_act_o : out std_logic; led_act_o : out std_logic;
...@@ -403,6 +406,8 @@ begin ...@@ -403,6 +406,8 @@ begin
wb_ack_o => wb_o.ack, wb_ack_o => wb_o.ack,
wb_stall_o => wb_o.stall, wb_stall_o => wb_o.stall,
rmon_events_o => rmon_events_o, rmon_events_o => rmon_events_o,
txts_o => txts_o, -- 2013-Nov-28 peterj added for debugging/calibration
rxts_o => rxts_o, -- 2013-Nov-28 peterj added for debugging/calibration
led_link_o => led_link_o, led_link_o => led_link_o,
led_act_o => led_act_o, led_act_o => led_act_o,
link_up_o => link_up_o, link_up_o => link_up_o,
......
modules/wrc_core/wr_core.vhd
View file @ 8bc0d374
...@@ -266,6 +266,12 @@ entity wr_core is ...@@ -266,6 +266,12 @@ entity wr_core is
txtsu_stb_o : out std_logic; txtsu_stb_o : out std_logic;
txtsu_ack_i : in std_logic := '1'; txtsu_ack_i : in std_logic := '1';
-----------------------------------------
-- Timestamp helper signals, used for Absolute Calibration
-----------------------------------------
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
----------------------------------------- -----------------------------------------
-- Pause Frame Control -- Pause Frame Control
----------------------------------------- -----------------------------------------
...@@ -776,6 +782,8 @@ begin ...@@ -776,6 +782,8 @@ begin
wb_i => ep_wb_in, wb_i => ep_wb_in,
wb_o => ep_wb_out, wb_o => ep_wb_out,
rmon_events_o => open, rmon_events_o => open,
txts_o => abscal_txts_o,
rxts_o => abscal_rxts_o,
fc_tx_pause_req_i => fc_tx_pause_req_i, fc_tx_pause_req_i => fc_tx_pause_req_i,
fc_tx_pause_delay_i => fc_tx_pause_delay_i, fc_tx_pause_delay_i => fc_tx_pause_delay_i,
fc_tx_pause_ready_o => fc_tx_pause_ready_o, fc_tx_pause_ready_o => fc_tx_pause_ready_o,
......
modules/wrc_core/wrcore_pkg.vhd
View file @ 8bc0d374
...@@ -445,6 +445,9 @@ package wrcore_pkg is ...@@ -445,6 +445,9 @@ package wrcore_pkg is
timestamps_o : out t_txtsu_timestamp; timestamps_o : out t_txtsu_timestamp;
timestamps_ack_i : in std_logic := '1'; timestamps_ack_i : in std_logic := '1';
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
fc_tx_pause_req_i : in std_logic := '0'; fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000"; fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic; fc_tx_pause_ready_o : out std_logic;
...@@ -661,6 +664,12 @@ package wrcore_pkg is ...@@ -661,6 +664,12 @@ package wrcore_pkg is
txtsu_stb_o : out std_logic; txtsu_stb_o : out std_logic;
txtsu_ack_i : in std_logic := '1'; txtsu_ack_i : in std_logic := '1';
-----------------------------------------
-- Timestamp helper signals, used for Absolute Calibration
-----------------------------------------
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
----------------------------------------- -----------------------------------------
-- Pause Frame Control -- Pause Frame Control
----------------------------------------- -----------------------------------------
......
modules/wrc_core/xwr_core.vhd
View file @ 8bc0d374
...@@ -216,6 +216,12 @@ entity xwr_core is ...@@ -216,6 +216,12 @@ entity xwr_core is
timestamps_o : out t_txtsu_timestamp; timestamps_o : out t_txtsu_timestamp;
timestamps_ack_i : in std_logic := '1'; timestamps_ack_i : in std_logic := '1';
-----------------------------------------
-- Timestamp helper signals, used for Absolute Calibration
-----------------------------------------
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
----------------------------------------- -----------------------------------------
-- Pause Frame Control -- Pause Frame Control
----------------------------------------- -----------------------------------------
...@@ -393,6 +399,9 @@ begin ...@@ -393,6 +399,9 @@ begin
txtsu_stb_o => timestamps_o.stb, txtsu_stb_o => timestamps_o.stb,
txtsu_ack_i => timestamps_ack_i, txtsu_ack_i => timestamps_ack_i,
abscal_txts_o => abscal_txts_o,
abscal_rxts_o => abscal_rxts_o,
fc_tx_pause_req_i => fc_tx_pause_req_i, fc_tx_pause_req_i => fc_tx_pause_req_i,
fc_tx_pause_delay_i => fc_tx_pause_delay_i, fc_tx_pause_delay_i => fc_tx_pause_delay_i,
fc_tx_pause_ready_o => fc_tx_pause_ready_o, fc_tx_pause_ready_o => fc_tx_pause_ready_o,
......
top/spec_ref_design/spec_wr_ref_top.vhd
View file @ 8bc0d374
...@@ -286,6 +286,8 @@ architecture top of spec_wr_ref_top is ...@@ -286,6 +286,8 @@ architecture top of spec_wr_ref_top is
signal onewire_oe : std_logic; signal onewire_oe : std_logic;
-- LEDs and GPIO -- LEDs and GPIO
signal wrc_abscal_txts_out : std_logic;
signal wrc_abscal_rxts_out : std_logic;
signal wrc_pps_out : std_logic; signal wrc_pps_out : std_logic;
signal wrc_pps_led : std_logic; signal wrc_pps_led : std_logic;
signal wrc_pps_in : std_logic; signal wrc_pps_in : std_logic;
...@@ -471,6 +473,9 @@ begin -- architecture top ...@@ -471,6 +473,9 @@ begin -- architecture top
wb_eth_master_o => cnx_master_out(c_WB_MASTER_ETHBONE), wb_eth_master_o => cnx_master_out(c_WB_MASTER_ETHBONE),
wb_eth_master_i => cnx_master_in(c_WB_MASTER_ETHBONE), wb_eth_master_i => cnx_master_in(c_WB_MASTER_ETHBONE),
abscal_txts_o => wrc_abscal_txts_out,
abscal_rxts_o => wrc_abscal_rxts_out,
pps_ext_i => wrc_pps_in, pps_ext_i => wrc_pps_in,
pps_p_o => wrc_pps_out, pps_p_o => wrc_pps_out,
...@@ -538,7 +543,8 @@ begin -- architecture top ...@@ -538,7 +543,8 @@ begin -- architecture top
wrc_pps_in <= dio_in(3); wrc_pps_in <= dio_in(3);
dio_out(0) <= wrc_pps_out; dio_out(0) <= wrc_pps_out;
dio_out(1) <= clk_ref_div2; dio_out(1) <= wrc_abscal_rxts_out;
dio_out(2) <= wrc_abscal_txts_out;
-- LEDs -- LEDs
U_Extend_PPS : gc_extend_pulse U_Extend_PPS : gc_extend_pulse
......
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