modules/endpoint: count rx frames at the end of rx_path chain and let…

modules/endpoint: count rx frames at the end of rx_path chain and let wr_endpoint decide which one to export It was usefull when debugging the SWcore on high traffic load.

modules/endpoint: count rx frames at the end of rx_path chain and let…
modules/endpoint: count rx frames at the end of rx_path chain and let wr_endpoint decide which one to export It was usefull when debugging the SWcore on high traffic load.
87e94134 · Grzegorz Daniluk · b5cb1c8c · 87e94134
Commit 87e94134 authored Jul 03, 2015 by Grzegorz Daniluk
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ep_rx_path.vhd modules/wr_endpoint/ep_rx_path.vhd +19 -1

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--- a/modules/wr_endpoint/ep_rx_path.vhd
+++ b/modules/wr_endpoint/ep_rx_path.vhd
@@ -170,6 +170,8 @@ architecture behavioral of ep_rx_path is
  signal rxbuf_full       : std_logic;
  signal rxbuf_dropped    : std_logic;
+  signal src_wb_out : t_wrf_source_out;
+  signal src_wb_cyc_d0 : std_logic;
 begin  -- behavioral
@@ -436,9 +438,11 @@ begin  -- behavioral
      snk_fab_i  => fab_pipe(9),
      snk_dreq_o => dreq_pipe(9),
      src_wb_i   => src_wb_i,
-      src_wb_o   => src_wb_o
+      src_wb_o   => src_wb_out
      );
+  src_wb_o <= src_wb_out;
  -- direct output of packet filter data (for TRU)
  pfilter_pclass_o <= pfilter_pclass;
  pfilter_drop_o   <= pfilter_drop;
@@ -470,5 +474,19 @@ begin  -- behavioral
  nice_dbg_o.pcs_fifo_afull <= pcs_fifo_almostfull;
  nice_dbg_o.rxbuf_full <= rxbuf_full;
+  process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if (rst_n_sys_i = '0') then
+        src_wb_cyc_d0 <= '0';
+      else
+        src_wb_cyc_d0 <= src_wb_out.cyc;
+      end if;
+    end if;
+  end process;
+  rmon_o.rx_frame <= '1' when (src_wb_out.cyc = '1' and src_wb_cyc_d0 = '0') else
+                     '0';
 end behavioral;