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White Rabbit core collection
Commit 7087a631 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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ep update

parent 245d5106
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Showing with 254 additions and 208 deletions
modules/wrsw_endpoint/endpoint_private_pkg.vhd
View file @ 7087a631
......@@ -28,11 +28,6 @@ package endpoint_private_pkg is
constant c_QMODE_PORT_TRUNK : std_logic_vector(1 downto 0) := "01";
constant c_QMODE_PORT_NONE : std_logic_vector(1 downto 0) := "11";
constant c_WRF_STATUS : std_logic_vector(1 downto 0) := "11";
constant c_WRF_DATA : std_logic_vector(1 downto 0) := "00";
constant c_WRF_OOB : std_logic_vector(1 downto 0) := "01";
-- fixme: remove these along with the non-WB version of the endpoint
constant c_wrsw_ctrl_none : std_logic_vector(4 - 1 downto 0) := x"0";
constant c_wrsw_ctrl_dst_mac : std_logic_vector(4 - 1 downto 0) := x"1";
......@@ -62,14 +57,6 @@ package endpoint_private_pkg is
end record;
type t_wrf_status_reg is record
is_hp : std_logic;
has_smac : std_logic;
has_crc : std_logic;
rx_error : std_logic;
match_class : std_logic_vector(7 downto 0);
end record;
component ep_1000basex_pcs
generic (
g_simulation : integer);
......@@ -289,9 +276,6 @@ package endpoint_private_pkg is
regs_b : inout t_ep_registers);
end component;
function f_marshall_wrf_status (stat : t_wrf_status_reg) return std_logic_vector;
function f_unmarshall_wrf_status(stat : std_logic_vector) return t_wrf_status_reg;
function f_encode_fabric_int (
data : std_logic_vector;
sof : std_logic;
......@@ -311,27 +295,6 @@ end endpoint_private_pkg;
package body endpoint_private_pkg is
function f_marshall_wrf_status(stat : t_wrf_status_reg)
return std_logic_vector is
variable tmp : std_logic_vector(15 downto 0);
begin
tmp(0) := stat.is_hp;
tmp(1) := stat.rx_error;
tmp(2) := stat.has_smac;
tmp(15 downto 8) := stat.match_class;
return tmp;
end function;
function f_unmarshall_wrf_status(stat : std_logic_vector) return t_wrf_status_reg is
variable tmp : t_wrf_status_reg;
begin
tmp.is_hp := stat(0);
tmp.rx_error := stat(1);
tmp.has_smac := stat(2);
tmp.match_class := stat(15 downto 8);
return tmp;
end function;
function f_encode_fabric_int (
data : std_logic_vector;
......
modules/wrsw_endpoint/ep_pcs_tbi_mdio_wb.vhd
View file @ 7087a631
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_pcs_tbi_mdio_wb.vhd
-- Author : auto-generated by wbgen2 from pcs_regs.wb
-- Created : Tue May 31 11:52:22 2011
-- Created : Thu Jun 9 00:58:47 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pcs_regs.wb
......
modules/wrsw_endpoint/ep_registers_pkg.vhd
View file @ 7087a631
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_registers_pkg.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created : Tue May 31 11:52:22 2011
-- Created : Thu Jun 9 00:58:47 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
......@@ -19,8 +19,8 @@ package ep_wbgen2_pkg is
type t_ep_registers is record
ecr_portid_o : std_logic_vector(4 downto 0);
ecr_rst_cnt_o : std_logic;
ecr_tx_en_fra_o : std_logic;
ecr_rx_en_fra_o : std_logic;
ecr_tx_en_o : std_logic;
ecr_rx_en_o : std_logic;
ecr_feat_vlan_i : std_logic;
ecr_feat_dmtd_i : std_logic;
ecr_feat_ptp_i : std_logic;
......@@ -32,11 +32,12 @@ package ep_wbgen2_pkg is
rfcr_a_runt_o : std_logic;
rfcr_a_giant_o : std_logic;
rfcr_a_hp_o : std_logic;
rfcr_a_frag_o : std_logic;
rfcr_qmode_o : std_logic_vector(1 downto 0);
rfcr_fix_prio_o : std_logic;
rfcr_prio_val_o : std_logic_vector(2 downto 0);
rfcr_vid_val_o : std_logic_vector(11 downto 0);
rfcr_keep_crc_o : std_logic;
rfcr_mru_o : std_logic_vector(13 downto 0);
vcr_qmode_o : std_logic_vector(1 downto 0);
vcr_fix_prio_o : std_logic;
vcr_prio_val_o : std_logic_vector(2 downto 0);
vcr_vid_val_o : std_logic_vector(11 downto 0);
fcr_rxpause_o : std_logic;
fcr_txpause_o : std_logic;
fcr_tx_thr_o : std_logic_vector(7 downto 0);
......@@ -65,8 +66,8 @@ package ep_wbgen2_pkg is
constant c_ep_registers_init_value: t_ep_registers := (
ecr_portid_o => (others => 'Z'),
ecr_rst_cnt_o => 'Z',
ecr_tx_en_fra_o => 'Z',
ecr_rx_en_fra_o => 'Z',
ecr_tx_en_o => 'Z',
ecr_rx_en_o => 'Z',
ecr_feat_vlan_i => 'Z',
ecr_feat_dmtd_i => 'Z',
ecr_feat_ptp_i => 'Z',
......@@ -78,11 +79,12 @@ package ep_wbgen2_pkg is
rfcr_a_runt_o => 'Z',
rfcr_a_giant_o => 'Z',
rfcr_a_hp_o => 'Z',
rfcr_a_frag_o => 'Z',
rfcr_qmode_o => (others => 'Z'),
rfcr_fix_prio_o => 'Z',
rfcr_prio_val_o => (others => 'Z'),
rfcr_vid_val_o => (others => 'Z'),
rfcr_keep_crc_o => 'Z',
rfcr_mru_o => (others => 'Z'),
vcr_qmode_o => (others => 'Z'),
vcr_fix_prio_o => 'Z',
vcr_prio_val_o => (others => 'Z'),
vcr_vid_val_o => (others => 'Z'),
fcr_rxpause_o => 'Z',
fcr_txpause_o => 'Z',
fcr_tx_thr_o => (others => 'Z'),
......
modules/wrsw_endpoint/ep_rx_crc_size_check.vhd
View file @ 7087a631
......@@ -5,6 +5,7 @@ use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all; -- for gc_crc_gen
use work.endpoint_private_pkg.all;
use work.ep_wbgen2_pkg.all;
-- 1st deframing pipeline stage - CRC/PCS error/Size checker
......@@ -55,7 +56,7 @@ architecture behavioral of ep_rx_crc_size_check is
signal crc_gen_reset : std_logic;
signal crc_match : std_logic;
signal byte_cntr : unsigned(11 downto 0);
signal byte_cntr : unsigned(13 downto 0);
signal is_runt : std_logic;
signal is_giant : std_logic;
signal size_check_ok : std_logic;
......@@ -146,7 +147,7 @@ begin -- behavioral
is_runt <= '0';
end if;
if(byte_cntr > unsigned(regs_b.rfcr_mru)) then
if(byte_cntr > unsigned(regs_b.rfcr_mru_o)) then
is_giant <= '1';
else
is_giant <= '0';
......@@ -156,8 +157,8 @@ begin -- behavioral
end if;
end process;
size_check_ok <= '0' when (is_runt = '1' and regs_b.rfcr_a_runt = '0') or
(is_giant = '1' and regs_b.rfcr_a_giant = '0') else '1';
size_check_ok <= '0' when (is_runt = '1' and regs_b.rfcr_a_runt_o = '0') or
(is_giant = '1' and regs_b.rfcr_a_giant_o = '0') else '1';
p_gen_output : process(clk_sys_i, rst_n_i)
......@@ -221,15 +222,15 @@ begin -- behavioral
src_eof <= '1';
end if;
if(regs_b.rfcr_keep_crc = '0') then
if(regs_b.rfcr_keep_crc_o = '0') then
valid_mask <= '0';
q_purge <= '1';
else
q_flush <= '1';
end if;
rmon_o.rx_runt <= is_runt and (not regs_b.rfcr_a_runt);
rmon_o.rx_giant <= is_giant and (not regs_b.rfcr_a_giant);
rmon_o.rx_runt <= is_runt and (not regs_b.rfcr_a_runt_o);
rmon_o.rx_giant <= is_giant and (not regs_b.rfcr_a_giant_o);
rmon_o.rx_crc_err <= not crc_match;
end if;
......
modules/wrsw_endpoint/ep_rx_deframer.vhd
View file @ 7087a631
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Last update: 2011-05-27
-- Last update: 2011-06-09
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -30,6 +30,7 @@ use ieee.numeric_std.all;
library work;
use work.endpoint_private_pkg.all;
use work.ep_wbgen2_pkg.all;
entity ep_rx_deframer is
......@@ -147,7 +148,7 @@ begin -- behavioral
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
enable_i => regs_b.ecr_rx_en,
enable_i => regs_b.ecr_rx_en_o,
snk_data_i => pcs_data_i,
snk_valid_i => pcs_valid_i,
snk_dreq_o => pcs_dreq_o,
......@@ -225,7 +226,7 @@ begin -- behavioral
counter <= (others => '0');
data_firstword <= '1';
if(regs_b.ecr_rx_en = '1') then
if(regs_b.ecr_rx_en_o = '1') then
if(snk_sof = '1') then
if(rbuf_drop_i = '0' and rtu_full_i = '0') then
state <= RXF_HEADER;
......@@ -428,7 +429,7 @@ begin -- behavioral
if(snk_eof = '1') then
if(oob_valid_i = '1' and regs_b.tscr_en_rxts = '1') then
if(oob_valid_i = '1' and regs_b.tscr_en_rxts_o = '1') then
state <= RXF_OOB;
counter <= (others => '0');
else
......
modules/wrsw_endpoint/ep_tx_framer.vhd
View file @ 7087a631
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Last update: 2011-05-28
-- Last update: 2011-06-09
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -26,14 +26,15 @@
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_private_pkg.all;
use work.ep_wbgen2_pkg.all;
entity ep_tx_framer is
......@@ -56,43 +57,9 @@ entity ep_tx_framer is
-- WRF Sink (see WRF specification for the details)
-------------------------------------------------------------------------------
-- TX data input
tx_data_i : in std_logic_vector(15 downto 0);
-- RX control bus: indicates type of word currently present on rx_data_o:
-- SRC_MAC, DST_MAC, VID_PRIO, PAYLOAD, CRC, OOB, END_OF_FRAME
tx_ctrl_i : in std_logic_vector(4 - 1 downto 0);
-- active HI: indicates the last byte of odd-sized frame. Byte is transferred
-- on MSB of tx_data_i.
tx_bytesel_i : in std_logic;
-- start of frame signal. HI pulse indicates the beginning of new frame. Upon
-- assertion of tx_sof_p_i, tx_ready_o shall become active, allowing the frame
-- data to be sent.
tx_sof_p1_i : in std_logic;
-- end-of-frame pulse: indicates end of the current frame on fabric i/f. When rx_valid_o
-- is active, rx_ctrl_o and rx_data_o contain the last data word of the current
-- frame.
tx_eof_p1_i : in std_logic;
-- active HI: TX fabric is ready to accept data.
tx_dreq_o : out std_logic;
-- active HI: indicates that tx_data_i, tx_ctrl_i, tx_bytesel_i are valid
tx_valid_i : in std_logic;
-- Source error: kept only for the comptibility with WRF spec. Ignored by the endpoint.
tx_rerror_p1_i : in std_logic;
-- TX abort: HI pulse immediately aborts transmission of current frame.
tx_tabort_p1_i : in std_logic;
-- TX error strobe: HI pulse indicates that an TX error occured. Error code is
-- present on tx_error_code_o.
tx_terror_p1_o : out std_logic;
snk_i: in t_wrf_sink_in;
snk_o: out t_wrf_sink_out;
-------------------------------------------------------------------------------
-- Flow Control Unit signals
-------------------------------------------------------------------------------
......@@ -158,11 +125,14 @@ architecture behavioral of ep_tx_framer is
-- Flow Control-related signals
signal tx_pause_mode : std_logic;
signal tx_pause_delay : std_logic_vector(15 downto 0);
signal ep_rfcr_qmode_i : std_logic_vector(1 downto 0) := c_QMODE_PORT_NONE;
signal ep_rfcr_qmode_i : std_logic_vector(1 downto 0) := c_QMODE_PORT_NONE;
signal sof_p1, eof_p1, abort_p1, rx_error_p1: std_logic;
signal snk_cyc_d0 : std_logic;
begin -- behavioral
crc_gen_reset <= '1' when rst_n_i = '0' else ((tx_sof_p1_i and (not tx_pause_mode)) or crc_gen_force_reset);
crc_gen_reset <= '1' when rst_n_i = '0' else ((sof_p1 and (not tx_pause_mode)) or crc_gen_force_reset);
crc_gen_enable <= q_valid and crc_gen_enable_mask;
U_tx_crc_generator : gc_crc_gen
......@@ -180,10 +150,25 @@ begin -- behavioral
rst_i => crc_gen_reset,
en_i => crc_gen_enable,
half_i => q_bytesel,
data_i => tx_data,
data_i => snk_i.dat,
match_o => open,
crc_o => crc_value);
p_detect_frame: process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i ='0' then
snk_cyc_d0 <= '0';
else
snk_cyc_d0 <= snk_i.cyc;
end if;
end process;
sof_p1 <= not snk_cyc_d0 and snk_i.cyc;
eof_p1 <= snk_cyc_d0 and not snk_i.cyc;
-- process: p_tx_fsm
-- inputs: everything
-- outputs: everything
......@@ -215,7 +200,7 @@ begin -- behavioral
-- we are in the middle of the frame and the framer has got suddenly
-- disabled or we've received an ABORT command or an error occured in the PCS:
if((state /= TXF_IDLE and state /= TXF_GAP) and (regs_b.ecr_tx_en = '0' or tx_tabort_p1_i = '1')) then
if((state /= TXF_IDLE and state /= TXF_GAP) and (regs_b.ecr_tx_en_o = '0' or tx_tabort_p1_i = '1')) then
-- abort the current frame
state <= TXF_ABORT;
tx_ready_t <= '0';
......@@ -245,7 +230,7 @@ begin -- behavioral
-- Check start-of-frame and send-pause signals and eventually
-- commence frame transmission
if((tx_sof_p1_i = '1' or tx_pause_i = '1') and regs_b.ecr_tx_en = '1') then
if((tx_sof_p1_i = '1' or tx_pause_i = '1') and regs_b.ecr_tx_en_o = '1') then
-- enable writing to PCS FIFO
q_eof <= '0';
write_mask <= '1';
......@@ -327,7 +312,7 @@ begin -- behavioral
-- SRC MAC bits [47:32]
when x"03" =>
if(tx_ctrl_i = c_wrsw_ctrl_none or tx_pause_mode = '1') then
tx_data <= regs_b.mach;
tx_data <= regs_b.mach_o;
else
tx_data <= tx_data_i;
end if;
......@@ -337,7 +322,7 @@ begin -- behavioral
-- SRC MAC bits [31:16]
when x"04" =>
if(tx_ctrl_i = c_wrsw_ctrl_none or tx_pause_mode = '1') then
tx_data <= regs_b.macl(31 downto 16);
tx_data <= regs_b.macl_o(31 downto 16);
else
tx_data <= tx_data_i;
end if;
......@@ -346,7 +331,7 @@ begin -- behavioral
-- SRC MAC bits [15:0]
when x"05" =>
if(tx_ctrl_i = c_wrsw_ctrl_none or tx_pause_mode = '1') then
tx_data <= regs_b.macl(15 downto 0);
tx_data <= regs_b.macl_o(15 downto 0);
else
tx_data <= tx_data_i;
end if;
......@@ -533,7 +518,7 @@ begin -- behavioral
end process;
tx_dreq_o <= tx_ready_t or (not regs_b.ecr_tx_en); -- /dev/null if disabled
tx_dreq_o <= tx_ready_t or (not regs_b.ecr_tx_en_o); -- /dev/null if disabled
pcs_data_o <= f_encode_fabric_int(
tx_data,
......
modules/wrsw_endpoint/ep_wishbone_controller.wb
View file @ 7087a631
......@@ -31,10 +31,10 @@ peripheral {
};
field {
name = "Transmit framer enable";
description = "1: TX framer is enabled\
0: TX framer is disabled";
prefix = "TX_EN_FRA";
name = "Transmit path enable";
description = "1: TX path is enabled\
0: TX path is disabled";
prefix = "TX_EN";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
......@@ -42,10 +42,10 @@ peripheral {
field {
name = "Receive deframer enable";
prefix = "RX_en_fra";
description = "1: RX deframer is enabled\
0: RX deframer is disabled";
name = "Receive path enable";
prefix = "RX_en";
description = "1: RX path is enabled\
0: RX path is disabled";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -182,15 +182,30 @@ peripheral {
};
field {
name = "RX accept fragments";
description = "1: endpoint accepts WhiteRabbit fragmented frames\
0: fragmented frames are dropped";
prefix = "a_frag";
name = "RX keep CRC";
description = "1: endpoint keeps FCS fields on the fabric side\
0: FCS fields are stripped";
prefix = "KEEP_CRC";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "Maximum receive unit (MRU)";
description = "Maximum size of a frame which is considered valid (in bytes)";
prefix = "MRU";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = SLV;
size = 14;
};
};
reg {
name = "VLAN control register";
prefix = "VCR";
field {
name = "RX 802.1q port mode";
description = "00: ACCESS port - tags untagged received packets with VID from RX_VID field. Drops all tagged packets not belonging to RX_VID VLAN\
......
modules/wrsw_endpoint/wr_fabric_pkg.vhd
View file @ 7087a631
library ieee;
use ieee.std_logic_1164.all;
package wr_fabric_pkg is
constant c_WRF_DATA : std_logic_vector(1 downto 0) := "00";
......@@ -5,6 +9,16 @@ package wr_fabric_pkg is
constant c_WRF_STATUS : std_logic_vector(1 downto 0) := "10";
constant c_WRF_USER : std_logic_vector(1 downto 0) := "11";
constant c_WRF_OOB_TYPE_RX : std_logic_vector(3 downto 0) := "0000";
constant c_WRF_OOB_TYPE_TX : std_logic_vector(3 downto 0) := "0001";
type t_wrf_oob is record
ts_r: std_logic_vector(27 downto 0);
ts_f: std_logic_vector(3 downto 0);
port_id: std_logic_vector(5 downto 0);
frame_id: std_logic_vector(15 downto 0);
end record;
type t_wrf_status_reg is record
is_hp : std_logic;
has_smac : std_logic;
......@@ -14,7 +28,7 @@ package wr_fabric_pkg is
match_class : std_logic_vector(7 downto 0);
end record;
type t_wrf_fromsource is record
type t_wrf_source_out is record
adr : std_logic_vector(1 downto 0);
dat : std_logic_vector(15 downto 0);
cyc : std_logic;
......@@ -23,9 +37,44 @@ package wr_fabric_pkg is
sel : std_logic_vector(1 downto 0);
end record;
type t_wrf_tosource is record
type t_wrf_source_in is record
ack : std_logic;
stall : std_logic;
end record;
subtype t_wrf_sink_in is t_wrf_source_out;
subtype t_wrf_sink_out is t_wrf_source_in;
function f_marshall_wrf_status (stat : t_wrf_status_reg) return std_logic_vector;
function f_unmarshall_wrf_status(stat : std_logic_vector) return t_wrf_status_reg;
end wr_fabric_pkg;
package body wr_fabric_pkg is
function f_marshall_wrf_status(stat : t_wrf_status_reg)
return std_logic_vector is
variable tmp : std_logic_vector(15 downto 0);
begin
tmp(0) := stat.is_hp;
tmp(1) := stat.rx_error;
tmp(2) := stat.has_smac;
tmp(15 downto 8) := stat.match_class;
return tmp;
end function;
function f_unmarshall_wrf_status(stat : std_logic_vector) return t_wrf_status_reg is
variable tmp : t_wrf_status_reg;
begin
tmp.is_hp := stat(0);
tmp.rx_error := stat(1);
tmp.has_smac := stat(2);
tmp.match_class := stat(15 downto 8);
return tmp;
end function;
end wr_fabric_pkg;
modules/wrsw_endpoint/wrsw_endpoint.vhd
View file @ 7087a631
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-26
-- Last update: 2011-05-31
-- Last update: 2011-06-09
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -75,23 +75,23 @@ entity wrsw_endpoint is
-- Xilinx GTP PHY Interace
-------------------------------------------------------------------------------
serdes_rst_o : out std_logic;
serdes_loopen_o : out std_logic;
serdes_prbsen_o : out std_logic;
serdes_enable_o : out std_logic;
serdes_syncen_o : out std_logic;
phy_rst_o : out std_logic;
phy_loopen_o : out std_logic;
phy_prbsen_o : out std_logic;
phy_enable_o : out std_logic;
phy_syncen_o : out std_logic;
-- serdes_tx_clk_i : in std_logic;
serdes_tx_data_o : out std_logic_vector(7 downto 0);
serdes_tx_k_o : out std_logic;
serdes_tx_disparity_i : in std_logic;
serdes_tx_enc_err_i : in std_logic;
phy_ref_clk_i: in std_logic;
phy_tx_data_o : out std_logic_vector(7 downto 0);
phy_tx_k_o : out std_logic;
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic;
serdes_rx_data_i : in std_logic_vector(7 downto 0);
serdes_rx_clk_i : in std_logic;
serdes_rx_k_i : in std_logic;
serdes_rx_enc_err_i : in std_logic;
serdes_rx_bitslide_i : in std_logic_vector(3 downto 0);
phy_rx_data_i : in std_logic_vector(7 downto 0);
phy_rx_clk_i : in std_logic;
phy_rx_k_i : in std_logic;
phy_rx_enc_err_i : in std_logic;
phy_rx_bitslide_i : in std_logic_vector(3 downto 0);
-------------------------------------------------------------------------------
-- WRF source (output of RXed packets)
......@@ -403,22 +403,22 @@ begin
link_ok_o => link_ok,
serdes_rst_o => serdes_rst_o,
serdes_loopen_o => serdes_loopen_o,
serdes_prbsen_o => serdes_prbsen_o,
serdes_enable_o => serdes_enable_o,
serdes_syncen_o => serdes_syncen_o,
serdes_tx_clk_i => clk_ref_i,
serdes_tx_data_o => serdes_tx_data_o,
serdes_tx_k_o => serdes_tx_k_o,
serdes_tx_disparity_i => serdes_tx_disparity_i,
serdes_tx_enc_err_i => serdes_tx_enc_err_i,
serdes_rx_data_i => serdes_rx_data_i,
serdes_rx_clk_i => serdes_rx_clk_i,
serdes_rx_k_i => serdes_rx_k_i,
serdes_rx_enc_err_i => serdes_rx_enc_err_i,
serdes_rx_bitslide_i => serdes_rx_bitslide_i,
serdes_rst_o => phy_rst_o,
serdes_loopen_o => phy_loopen_o,
serdes_prbsen_o => phy_prbsen_o,
serdes_enable_o => phy_enable_o,
serdes_syncen_o => phy_syncen_o,
serdes_tx_clk_i => phy_ref_clk_i,
serdes_tx_data_o => phy_tx_data_o,
serdes_tx_k_o => phy_tx_k_o,
serdes_tx_disparity_i => phy_tx_disparity_i,
serdes_tx_enc_err_i => phy_tx_enc_err_i,
serdes_rx_data_i => phy_rx_data_i,
serdes_rx_clk_i => phy_rx_clk_i,
serdes_rx_k_i => phy_rx_k_i,
serdes_rx_enc_err_i => phy_rx_enc_err_i,
serdes_rx_bitslide_i => phy_rx_bitslide_i,
rmon_o => rmon,
......@@ -643,7 +643,7 @@ begin
clk_sys_i => clk_sys_i,
clk_a_i => clk_ref_i,
clk_b_i => serdes_rx_clk_i,
clk_b_i => phy_rx_clk_i,
clk_dmtd_i => clk_dmtd_i,
rst_n_i => rst_n_i,
......
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