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White Rabbit core collection
Commit 245d5106 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wishbonized endpoint (wip)

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modules/wrsw_endpoint/Manifest.py
View file @ 245d5106
files = ["endpoint_pkg.vhd",
"ep_enc_8b10b.vhd",
"ep_dec_8b10b.vhd",
"ep_rx_pcs_tbi.vhd",
"ep_tx_pcs_tbi.vhd",
"ep_autonegotiation.vhd",
"ep_pcs_tbi_mdio_wb.vhd",
"ep_1000basex_pcs.vhd",
"ep_rx_crc_size_check.vhd",
"ep_rx_deframer.vhd",
"ep_tx_framer.vhd",
"ep_flow_control.vhd",
"ep_timestamping_unit.vhd",
"ep_rmon_counters.vhd",
"ep_rx_buffer.vhd",
"ep_sync_detect.vhd",
"ep_wishbone_controller.vhd",
"ep_ts_counter.vhd",
"wrsw_endpoint.vhd"
];
files = [ "endpoint_private_pkg.vhd",
"ep_rx_pcs_tbi.vhd",
"ep_tx_pcs_tbi.vhd",
"ep_autonegotiation.vhd",
"ep_pcs_tbi_mdio_wb.vhd",
"ep_1000basex_pcs.vhd",
"ep_rx_crc_size_check.vhd",
"ep_crc_bypass_queue.vhd",
"ep_rx_deframer.vhd",
"ep_tx_framer.vhd",
"ep_flow_control.vhd",
"ep_timestamping_unit.vhd",
"ep_rmon_counters.vhd",
"ep_rx_buffer.vhd",
"ep_sync_detect.vhd",
"ep_wishbone_controller.vhd",
"ep_ts_counter.vhd",
"wrsw_endpoint.vhd",
"ep_registers_pkg.vhd"
];
modules/wrsw_endpoint/build_wb.sh
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#!/bin/bash
mkdir -p doc
wbgen2 -D ./doc/wrsw_endpoint.html -V ep_wishbone_controller.vhd -C ../../../software/include/hw/endpoint_regs.h --cstyle defines --lang vhdl -K ../../sim/endpoint_regs.v ep_wishbone_controller.wb
~/wbgen2/wishbone-gen/wbgen2 -D ./doc/wrsw_endpoint.html -p ep_registers_pkg.vhd -H record -V ep_wishbone_controller.vhd -C ../../../software/include/hw/endpoint_regs.h --cstyle defines --lang vhdl -K ../../sim/endpoint_regs.v ep_wishbone_controller.wb
wbgen2 -D ./doc/wrsw_endpoint_mdio.html -V ep_pcs_tbi_mdio_wb.vhd -C ../../../software/include/hw/endpoint_mdio.h --cstyle defines --lang vhdl -K ../../sim/endpoint_mdio.v pcs_regs.wb
\ No newline at end of file
modules/wrsw_endpoint/endpoint_private_pkg.vhd 0 → 100644
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modules/wrsw_endpoint/ep_1000basex_pcs.vhd
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modules/wrsw_endpoint/ep_autonegotiation.vhd
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......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-02-07
-- Last update: 2011-05-27
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -46,7 +46,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.endpoint_pkg.all;
use work.endpoint_private_pkg.all;
entity ep_autonegotiation is
generic (
......
modules/wrsw_endpoint/ep_flow_control.vhd
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......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-02-07
-- Last update: 2011-05-27
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -44,7 +44,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.endpoint_pkg.all;
use work.endpoint_private_pkg.all;
entity ep_flow_control is
......
modules/wrsw_endpoint/ep_packet_filter.vhd 0 → 100644
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
use work.wr_fabric_pkg.all;
entity ep_packet_filter is
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
snk_data_i: in std_logic_vector(17 downto 0);
snk_valid_i: in std_logic;
snk_dreq_o: out std_logic;
src_data_o: out std_logic_vector(17 downto 0);
src_valid_o : out std_logic(17 downto 0);
src_dreq_i: in std_logic;
match_done_o: out std_logic;
match_class_o: out std_logic_vector(7 downto 0);
regs_b: inout t_ep_registers
);
end ep_packet_filter;
architecture behavioral of ep_packet_filter is
constant c_BACKLOG_SIZE : integer := 128;
constant c_BACKLOG_SIZE_LOG2 : integer := 7;
constant c_OPC_AND : std_logic_vector(1 downto 0) : = "00";
constant c_OPC_OR : std_logic_vector(1 downto 0) : = "01";
constant c_OPC_XOR : std_logic_vector(1 downto 0) : = "10";
constant c_OPC_FIN : std_logic_vector(1 downto 0) := "11";
type t_microcode_instruction is record
-- comparison value
cmp_val : std_logic_vector(15 downto 0);
-- comparison mask (nibbles)
cmp_mask : std_logic_vector(3 downto 0);
-- comparison offset (0 = 1st word of the frame)
cmp_offset : std_logic_vector(5 downto 0); -- 26
-- opcode
cmp_en: std_logic;
opcode : std_logic_vector(1 downto 0);
op_b : std_logic_vector(4 downto 0);
op_dst : std_logic_vector(4 downto 0);
end record;
signal fifo_wr_ptr : unsigned(c_BACKLOG_SIZE_LOG2 - 1 downto 0);
signal fifo_rd_ptr : unsigned(c_BACKLOG_SIZE_LOG2 - 1 downto 0);
signal fifo_full : std_logic;
signal fifo_next_wr_ptr : unsigned(c_BACKLOG_SIZE_LOG2 -1 downto 0);
signal fifo_next_rd_ptr : unsigned(c_BACKLOG_SIZE_LOG2 -1 downto 0);
signal pc : unsigned(c_BACKLOG_SIZE_LOG2-1 downto 0);
signal op : t_microcode_instruction;
signal R : std_logic_vector(31 downto 0);
begin -- behavioral
R(0) <= '0';
R(1) <= '1';
snk_o.stall <= src_i.stall or fifo_full;
fifo_next_rd_ptr <= fifo_rd_ptr + 1;
fifo_next_wr_ptr <= fifo_wr_ptr + 1;
fifo_full <= '1' when fifo_next_wr_ptr = fifo_rd_ptr else '0';
end behavioral;
modules/wrsw_endpoint/ep_pcs_tbi_mdio_wb.vhd
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......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_pcs_tbi_mdio_wb.vhd
-- Author : auto-generated by wbgen2 from pcs_regs.wb
-- Created : Tue Dec 7 17:14:23 2010
-- Created : Tue May 31 11:52:22 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pcs_regs.wb
......
modules/wrsw_endpoint/ep_registers_pkg.vhd 0 → 100644
View file @ 245d5106
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for WR switch endpoint controller
---------------------------------------------------------------------------------------
-- File : ep_registers_pkg.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created : Tue May 31 11:52:22 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
package ep_wbgen2_pkg is
type t_ep_registers is record
ecr_portid_o : std_logic_vector(4 downto 0);
ecr_rst_cnt_o : std_logic;
ecr_tx_en_fra_o : std_logic;
ecr_rx_en_fra_o : std_logic;
ecr_feat_vlan_i : std_logic;
ecr_feat_dmtd_i : std_logic;
ecr_feat_ptp_i : std_logic;
ecr_feat_dpi_i : std_logic;
tscr_en_txts_o : std_logic;
tscr_en_rxts_o : std_logic;
tscr_cs_start_o : std_logic;
tscr_cs_done_i : std_logic;
rfcr_a_runt_o : std_logic;
rfcr_a_giant_o : std_logic;
rfcr_a_hp_o : std_logic;
rfcr_a_frag_o : std_logic;
rfcr_qmode_o : std_logic_vector(1 downto 0);
rfcr_fix_prio_o : std_logic;
rfcr_prio_val_o : std_logic_vector(2 downto 0);
rfcr_vid_val_o : std_logic_vector(11 downto 0);
fcr_rxpause_o : std_logic;
fcr_txpause_o : std_logic;
fcr_tx_thr_o : std_logic_vector(7 downto 0);
fcr_tx_quanta_o : std_logic_vector(15 downto 0);
mach_o : std_logic_vector(15 downto 0);
macl_o : std_logic_vector(31 downto 0);
dmcr_en_o : std_logic;
dmcr_n_avg_o : std_logic_vector(11 downto 0);
dmsr_ps_val_i : std_logic_vector(23 downto 0);
dmsr_ps_rdy_o : std_logic;
dmsr_ps_rdy_i : std_logic;
dmsr_ps_rdy_load_o : std_logic;
mdio_cr_data_o : std_logic_vector(15 downto 0);
mdio_cr_data_wr_o : std_logic;
mdio_cr_addr_o : std_logic_vector(7 downto 0);
mdio_cr_rw_o : std_logic;
mdio_sr_rdata_i : std_logic_vector(15 downto 0);
mdio_sr_phyad_o : std_logic_vector(7 downto 0);
mdio_sr_ready_i : std_logic;
dsr_lstatus_i : std_logic;
dsr_lact_o : std_logic;
dsr_lact_i : std_logic;
dsr_lact_load_o : std_logic;
end record;
constant c_ep_registers_init_value: t_ep_registers := (
ecr_portid_o => (others => 'Z'),
ecr_rst_cnt_o => 'Z',
ecr_tx_en_fra_o => 'Z',
ecr_rx_en_fra_o => 'Z',
ecr_feat_vlan_i => 'Z',
ecr_feat_dmtd_i => 'Z',
ecr_feat_ptp_i => 'Z',
ecr_feat_dpi_i => 'Z',
tscr_en_txts_o => 'Z',
tscr_en_rxts_o => 'Z',
tscr_cs_start_o => 'Z',
tscr_cs_done_i => 'Z',
rfcr_a_runt_o => 'Z',
rfcr_a_giant_o => 'Z',
rfcr_a_hp_o => 'Z',
rfcr_a_frag_o => 'Z',
rfcr_qmode_o => (others => 'Z'),
rfcr_fix_prio_o => 'Z',
rfcr_prio_val_o => (others => 'Z'),
rfcr_vid_val_o => (others => 'Z'),
fcr_rxpause_o => 'Z',
fcr_txpause_o => 'Z',
fcr_tx_thr_o => (others => 'Z'),
fcr_tx_quanta_o => (others => 'Z'),
mach_o => (others => 'Z'),
macl_o => (others => 'Z'),
dmcr_en_o => 'Z',
dmcr_n_avg_o => (others => 'Z'),
dmsr_ps_val_i => (others => 'Z'),
dmsr_ps_rdy_o => 'Z',
dmsr_ps_rdy_i => 'Z',
dmsr_ps_rdy_load_o => 'Z',
mdio_cr_data_o => (others => 'Z'),
mdio_cr_data_wr_o => 'Z',
mdio_cr_addr_o => (others => 'Z'),
mdio_cr_rw_o => 'Z',
mdio_sr_rdata_i => (others => 'Z'),
mdio_sr_phyad_o => (others => 'Z'),
mdio_sr_ready_i => 'Z',
dsr_lstatus_i => 'Z',
dsr_lact_o => 'Z',
dsr_lact_i => 'Z',
dsr_lact_load_o => 'Z'
);
end package;
modules/wrsw_endpoint/ep_rmon_counters.vhd
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......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-02-09
-- Last update: 2011-05-27
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -44,7 +44,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.endpoint_pkg.all;
use work.endpoint_private_pkg.all;
entity ep_rmon_counters is
......
modules/wrsw_endpoint/ep_rx_buffer.vhd
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......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-26
-- Last update: 2011-05-11
-- Last update: 2011-05-27
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -26,8 +26,8 @@ use ieee.numeric_std.all;
library work;
use work.endpoint_pkg.all;
use work.genram_pkg.all;
use work.endpoint_private_pkg.all;
entity ep_rx_buffer is
generic (
......
modules/wrsw_endpoint/ep_rx_deframer.vhd
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modules/wrsw_endpoint/ep_rx_pcs_tbi.vhd
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modules/wrsw_endpoint/ep_sync_detect.vhd
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......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-05-28
-- Last update: 2011-02-04
-- Last update: 2011-05-27
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -27,7 +27,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.endpoint_pkg.all;
use work.endpoint_private_pkg.all;
entity ep_sync_detect is
......
modules/wrsw_endpoint/ep_timestamping_unit.vhd
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......@@ -35,7 +35,7 @@ use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
use work.endpoint_pkg.all;
use work.endpoint_private_pkg.all;
entity ep_timestamping_unit is
generic (
......
modules/wrsw_endpoint/ep_ts_counter.vhd
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......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Last update: 2010-09-17
-- Last update: 2011-05-27
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -29,7 +29,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.endpoint_pkg.all;
use work.endpoint_private_pkg.all;
entity ep_ts_counter is
......
modules/wrsw_endpoint/ep_tx_framer.vhd
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modules/wrsw_endpoint/ep_tx_pcs_tbi.vhd
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modules/wrsw_endpoint/ep_wishbone_controller.wb
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......@@ -5,7 +5,7 @@ peripheral {
name = "WR switch endpoint controller";
description = "EP controller";
hdl_entity = "ep_wishbone_controller";
prefix = "EP";
prefix = "ep";
-- ECR
reg {
......@@ -51,6 +51,51 @@ peripheral {
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "Feature present: VLAN tagging";
description = "1: this implementation of WR Endpoint supports VLAN processing \
(tagging/untagging). VCR register can be used to control the \
VLAN functionality \
0: no VLAN support compiled";
prefix = "FEAT_VLAN";
align = 24;
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Feature present: DDMTD phase measurement";
description = "1: this implementation of WR Endpoint can do fine phase measurements \
using a DDMTD phase detector\
0: no phase measurement support compiled";
prefix = "FEAT_DMTD";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Feature present: IEEE1588 timestamper";
description = "1: this implementation of WR Endpoint can timestamp packets\
0: no timestamping compiled";
prefix = "FEAT_PTP";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Feature present: DPI packet classifier";
description = "1: this implementation of WR Endpoint includes Deep Packet Inspection packet classifier/filter\
0: no DPI compiled";
prefix = "FEAT_DPI";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
......@@ -356,7 +401,7 @@ peripheral {
};
reg {
name = "MDIO Status Register";
name = "MDIO Address/Status Register";
description = "Register with the current status of the MDIO interface";
prefix = "MDIO_SR";
......@@ -370,6 +415,16 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "MDIO PHY Address";
description = "Address of the PHY on the MDIO bus";
prefix = "PHYAD";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "MDIO Ready";
......
modules/wrsw_endpoint/wr_fabric_pkg.vhd 0 → 100644
View file @ 245d5106
package wr_fabric_pkg is
constant c_WRF_DATA : std_logic_vector(1 downto 0) := "00";
constant c_WRF_OOB : std_logic_vector(1 downto 0) := "01";
constant c_WRF_STATUS : std_logic_vector(1 downto 0) := "10";
constant c_WRF_USER : std_logic_vector(1 downto 0) := "11";
type t_wrf_status_reg is record
is_hp : std_logic;
has_smac : std_logic;
has_crc : std_logic;
rx_error : std_logic;
tag_me : std_logic;
match_class : std_logic_vector(7 downto 0);
end record;
type t_wrf_fromsource is record
adr : std_logic_vector(1 downto 0);
dat : std_logic_vector(15 downto 0);
cyc : std_logic;
stb : std_logic;
we : std_logic;
sel : std_logic_vector(1 downto 0);
end record;
type t_wrf_tosource is record
ack : std_logic;
stall : std_logic;
end record;
end wr_fabric_pkg;
modules/wrsw_endpoint/wrsw_endpoint.vhd
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