Skip to content

W
White Rabbit core collection
Commit 6f4529b4 authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files
Options

board/common: introduce common wrapper for shared features across supported boards

parent b01bf0e5
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 853 additions and 607 deletions
board/common/Manifest.py 0 → 100644
View file @ 6f4529b4
files = [
"wr_board_pkg.vhd",
"xwrc_board_common.vhd",
]
board/common/wr_board_pkg.vhd 0 → 100644
View file @ 6f4529b4
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.wrcore_pkg.all;
package wr_board_pkg is
type t_board_fabric_iface is (PLAIN, STREAMERS, ETHERBONE, always_last_invalid);
procedure f_check_fabric_iface_type (
constant iface_type : in t_board_fabric_iface);
function f_str2iface_type (
constant iface_str : string)
return t_board_fabric_iface;
component xwrc_board_common is
generic (
g_simulation : integer;
g_with_external_clock_input : boolean;
g_phys_uart : boolean;
g_virtual_uart : boolean;
g_aux_clks : integer;
g_ep_rxbuf_size : integer;
g_tx_runt_padding : boolean;
g_dpram_initf : string;
g_dpram_size : integer;
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_aux_sdb : t_sdb_device;
g_softpll_enable_debugger : boolean;
g_vuart_fifo_size : integer;
g_pcs_16bit : boolean;
g_diag_id : integer;
g_diag_ver : integer;
g_diag_ro_size : integer;
g_diag_rw_size : integer;
g_streamer_width : integer;
g_fabric_iface : t_board_fabric_iface);
port (
clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_ref_i : in std_logic;
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_ext_i : in std_logic := '0';
clk_ext_mul_i : in std_logic := '0';
clk_ext_mul_locked_i : in std_logic := '1';
clk_ext_stopped_i : in std_logic := '0';
clk_ext_rst_o : out std_logic;
pps_ext_i : in std_logic := '0';
rst_n_i : in std_logic;
dac_hpll_load_p1_o : out std_logic;
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_dpll_load_p1_o : out std_logic;
dac_dpll_data_o : out std_logic_vector(15 downto 0);
phy8_o : out t_phy_8bits_from_wrc;
phy8_i : in t_phy_8bits_to_wrc := c_dummy_phy8_to_wrc;
phy16_o : out t_phy_16bits_from_wrc;
phy16_i : in t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
led_act_o : out std_logic;
led_link_o : out std_logic;
scl_o : out std_logic;
scl_i : in std_logic := '1';
sda_o : out std_logic;
sda_i : in std_logic := '1';
sfp_scl_o : out std_logic;
sfp_scl_i : in std_logic := '1';
sfp_sda_o : out std_logic;
sfp_sda_i : in std_logic := '1';
sfp_det_i : in std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic := '0';
uart_rxd_i : in std_logic := '0';
uart_txd_o : out std_logic;
owr_pwren_o : out std_logic_vector(1 downto 0);
owr_en_o : out std_logic_vector(1 downto 0);
owr_i : in std_logic_vector(1 downto 0) := (others => '1');
slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
slave_o : out t_wishbone_slave_out;
aux_master_o : out t_wishbone_master_out;
aux_master_i : in t_wishbone_master_in := cc_dummy_master_in;
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_dummy_snk_in;
wrs_tx_data_i : in std_logic_vector(g_streamer_width-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_streamer_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wb_eth_master_o : out t_wishbone_master_out;
wb_eth_master_i : in t_wishbone_master_in := cc_dummy_master_in;
timestamps_o : out t_txtsu_timestamp;
timestamps_ack_i : in std_logic := '1';
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
tm_link_up_o : out std_logic;
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
pps_p_o : out std_logic;
pps_led_o : out std_logic;
link_ok_o : out std_logic);
end component xwrc_board_common;
end wr_board_pkg;
package body wr_board_pkg is
procedure f_check_fabric_iface_type (
constant iface_type : in t_board_fabric_iface) is
begin
if iface_type >= always_last_invalid then
assert FALSE
report "WR PTP core fabric interface [" & t_board_fabric_iface'image(iface_type) & "] is not supported"
severity ERROR;
end if;
end procedure f_check_fabric_iface_type;
function f_str2iface_type (
constant iface_str : string)
return t_board_fabric_iface is
variable result : t_board_fabric_iface;
begin
case iface_str is
when "PLAINFBRC" => result := PLAIN;
when "STREAMERS" => result := STREAMERS;
when "ETHERBONE" => result := ETHERBONE;
when others => result := always_last_invalid;
end case;
return result;
end function f_str2iface_type;
end package body wr_board_pkg;
board/common/xwrc_board_common.vhd 0 → 100644
View file @ 6f4529b4
This diff is collapsed.
board/spec/Manifest.py
View file @ 6f4529b4
......@@ -3,3 +3,9 @@ files = [
"xwrc_board_spec.vhd",
"wrc_board_spec.vhd",
]
modules = {
"local" : [
"../common",
]
}
board/spec/wr_spec_pkg.vhd
View file @ 6f4529b4
......@@ -4,16 +4,17 @@ use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
use work.wr_board_pkg.all;
package wr_spec_pkg is
component xwrc_board_spec is
generic (
g_simulation : integer := 0;
g_with_external_clock_input : boolean := TRUE;
g_fabric_iface : string := "plainfbrc";
g_streamer_width : integer := 32;
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram");
g_simulation : integer := 0;
g_with_external_clock_input : boolean := TRUE;
g_fabric_iface : t_board_fabric_iface := PLAIN;
g_streamer_width : integer := 32;
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram");
port (
areset_n_i : in std_logic;
clk_20m_vcxo_i : in std_logic;
......@@ -21,7 +22,7 @@ package wr_spec_pkg is
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp_n_i : in std_logic;
clk_125m_gtp_p_i : in std_logic;
clk_10m_ext_ref_i : in std_logic := '0';
clk_10m_ext_ref_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
rst_62m5_n_o : out std_logic;
......@@ -34,15 +35,15 @@ package wr_spec_pkg is
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_det_i : in std_logic := '1';
sfp_det_i : in std_logic := '1';
sfp_sda_i : in std_logic;
sfp_sda_o : out std_logic;
sfp_scl_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
sfp_los_i : in std_logic := '0';
eeprom_sda_i : in std_logic;
eeprom_sda_o : out std_logic;
eeprom_scl_i : in std_logic;
......@@ -62,15 +63,15 @@ package wr_spec_pkg is
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_dummy_snk_in;
wrs_tx_data_i : in std_logic_vector(g_streamer_width-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_streamer_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wrs_rx_dreq_i : in std_logic := '0';
wb_eth_master_o : out t_wishbone_master_out;
wb_eth_master_i : in t_wishbone_master_in := cc_dummy_master_in;
pps_ext_i : in std_logic;
......@@ -87,7 +88,7 @@ package wr_spec_pkg is
generic (
g_simulation : integer := 0;
g_with_external_clock_input : integer := 1;
g_fabric_iface : string := "plain";
g_fabric_iface : string := "PLAINFBRC";
g_streamer_width : integer := 32;
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram");
port (
......@@ -97,7 +98,7 @@ package wr_spec_pkg is
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp_n_i : in std_logic;
clk_125m_gtp_p_i : in std_logic;
clk_10m_ext_ref_i : in std_logic := '0';
clk_10m_ext_ref_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
rst_62m5_n_o : out std_logic;
......@@ -110,15 +111,15 @@ package wr_spec_pkg is
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_det_i : in std_logic := '1';
sfp_det_i : in std_logic := '1';
sfp_sda_i : in std_logic;
sfp_sda_o : out std_logic;
sfp_scl_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
sfp_los_i : in std_logic := '0';
eeprom_sda_i : in std_logic;
eeprom_sda_o : out std_logic;
eeprom_scl_i : in std_logic;
......@@ -135,9 +136,9 @@ package wr_spec_pkg is
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_address_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_err_o : out std_logic;
......@@ -164,15 +165,15 @@ package wr_spec_pkg is
wrf_snk_err_o : out std_logic;
wrf_snk_rty_o : out std_logic;
wrs_tx_data_i : in std_logic_vector(g_streamer_width-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_streamer_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wrs_rx_dreq_i : in std_logic := '0';
wb_eth_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_eth_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_eth_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
......@@ -180,11 +181,11 @@ package wr_spec_pkg is
wb_eth_we_o : out std_logic;
wb_eth_cyc_o : out std_logic;
wb_eth_stb_o : out std_logic;
wb_eth_ack_i : in std_logic := '0';
wb_eth_int_i : in std_logic := '0';
wb_eth_err_i : in std_logic := '0';
wb_eth_rty_i : in std_logic := '0';
wb_eth_stall_i : in std_logic := '0';
wb_eth_ack_i : in std_logic := '0';
wb_eth_int_i : in std_logic := '0';
wb_eth_err_i : in std_logic := '0';
wb_eth_rty_i : in std_logic := '0';
wb_eth_stall_i : in std_logic := '0';
pps_ext_i : in std_logic;
pps_p_o : out std_logic;
pps_led_o : out std_logic;
......
board/spec/wrc_board_spec.vhd
View file @ 6f4529b4
......@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2016-02-17
-- Last update: 2017-02-17
-- Last update: 2017-02-22
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -50,6 +50,7 @@ use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.streamers_pkg.all;
use work.wr_xilinx_pkg.all;
use work.wr_board_pkg.all;
use work.wr_spec_pkg.all;
entity wrc_board_spec is
......@@ -58,10 +59,10 @@ entity wrc_board_spec is
g_simulation : integer := 0;
-- Select whether to include external ref clock input
g_with_external_clock_input : integer := 1;
-- "plain" = expose WRC fabric interface
-- "plainfbrc" = expose WRC fabric interface
-- "streamers" = attach WRC streamers to fabric interface
-- "etherbone" = attach Etherbone slave to fabric interface
g_fabric_iface : string := "plain";
g_fabric_iface : string := "plainfbrc";
-- data width when g_fabric_iface = "streamers" (otherwise ignored)
g_streamer_width : integer := 32;
-- memory initialisation file for embedded CPU
......@@ -325,7 +326,7 @@ begin -- architecture struct
generic map (
g_simulation => g_simulation,
g_with_external_clock_input => f_int2bool(g_with_external_clock_input),
g_fabric_iface => g_fabric_iface,
g_fabric_iface => f_str2iface_type(g_fabric_iface),
g_streamer_width => g_streamer_width,
g_dpram_initf => g_dpram_initf)
port map (
......
board/spec/xwrc_board_spec.vhd
View file @ 6f4529b4
This diff is collapsed.
board/svec/Manifest.py
View file @ 6f4529b4
......@@ -3,3 +3,9 @@ files = [
"xwrc_board_svec.vhd",
"wrc_board_svec.vhd",
]
modules = {
"local" : [
"../common",
]
}
board/svec/wr_svec_pkg.vhd
View file @ 6f4529b4
......@@ -4,16 +4,17 @@ use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
use work.wr_board_pkg.all;
package wr_svec_pkg is
component xwrc_board_svec is
generic (
g_simulation : integer := 0;
g_with_external_clock_input : boolean := TRUE;
g_fabric_iface : string := "plainfbrc";
g_streamer_width : integer := 32;
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram");
g_simulation : integer := 0;
g_with_external_clock_input : boolean := TRUE;
g_fabric_iface : t_board_fabric_iface := PLAIN;
g_streamer_width : integer := 32;
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram");
port (
areset_n_i : in std_logic;
clk_20m_vcxo_i : in std_logic;
......@@ -88,7 +89,7 @@ package wr_svec_pkg is
generic (
g_simulation : integer := 0;
g_with_external_clock_input : integer := 1;
g_fabric_iface : string := "plain";
g_fabric_iface : string := "PLAINFBRC";
g_streamer_width : integer := 32;
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram");
port (
......
board/svec/wrc_board_svec.vhd
View file @ 6f4529b4
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2016-02-16
-- Last update: 2017-02-20
-- Last update: 2017-02-22
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -50,6 +50,7 @@ use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.streamers_pkg.all;
use work.wr_xilinx_pkg.all;
use work.wr_board_pkg.all;
use work.wr_svec_pkg.all;
entity wrc_board_svec is
......@@ -58,10 +59,10 @@ entity wrc_board_svec is
g_simulation : integer := 0;
-- Select whether to include external ref clock input
g_with_external_clock_input : integer := 1;
-- "plain" = expose WRC fabric interface
-- "plainfbrc" = expose WRC fabric interface
-- "streamers" = attach WRC streamers to fabric interface
-- "etherbone" = attach Etherbone slave to fabric interface
g_fabric_iface : string := "plain";
g_fabric_iface : string := "plainfbrc";
-- data width when g_fabric_iface = "streamers" (otherwise ignored)
g_streamer_width : integer := 32;
-- memory initialisation file for embedded CPU
......@@ -327,7 +328,7 @@ begin -- architecture struct
generic map (
g_simulation => g_simulation,
g_with_external_clock_input => f_int2bool(g_with_external_clock_input),
g_fabric_iface => g_fabric_iface,
g_fabric_iface => f_str2iface_type(g_fabric_iface),
g_streamer_width => g_streamer_width,
g_dpram_initf => g_dpram_initf)
port map (
......
board/svec/xwrc_board_svec.vhd
View file @ 6f4529b4
This diff is collapsed.
board/vfchd/Manifest.py
View file @ 6f4529b4
......@@ -4,3 +4,9 @@ files = [
"wrc_board_vfchd.vhd",
"sfp_i2c_adapter.vhd",
]
modules = {
"local" : [
"../common",
]
}
board/vfchd/wr_vfchd_pkg.vhd
View file @ 6f4529b4
......@@ -4,17 +4,18 @@ use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
use work.wr_board_pkg.all;
package wr_vfchd_pkg is
component xwrc_board_vfchd is
generic (
g_simulation : integer := 0;
g_with_external_clock_input : boolean := TRUE;
g_pcs_16bit : boolean := FALSE;
g_fabric_iface : string := "plain";
g_streamer_width : integer := 32;
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.mif");
g_simulation : integer := 0;
g_with_external_clock_input : boolean := TRUE;
g_pcs_16bit : boolean := FALSE;
g_fabric_iface : t_board_fabric_iface := PLAIN;
g_streamer_width : integer := 32;
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.mif");
port (
clk_board_125m_i : in std_logic;
clk_board_20m_i : in std_logic;
......@@ -73,7 +74,7 @@ package wr_vfchd_pkg is
g_simulation : integer := 0;
g_with_external_clock_input : integer := 1;
g_pcs_16bit : integer := 0;
g_fabric_iface : string := "plain";
g_fabric_iface : string := "PLAINFBRC";
g_streamer_width : integer := 32;
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.mif");
port (
......
board/vfchd/wrc_board_vfchd.vhd
View file @ 6f4529b4
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2016-07-26
-- Last update: 2017-02-20
-- Last update: 2017-02-22
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -50,6 +50,7 @@ use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.streamers_pkg.all;
use work.wr_altera_pkg.all;
use work.wr_board_pkg.all;
use work.wr_vfchd_pkg.all;
entity wrc_board_vfchd is
......@@ -60,10 +61,10 @@ entity wrc_board_vfchd is
g_with_external_clock_input : integer := 1;
-- set to 1 to use 16bit PCS (instead of default 8bit PCS)
g_pcs_16bit : integer := 0;
-- "plain" = expose WRC fabric interface
-- "plainfbrc" = expose WRC fabric interface
-- "streamers" = attach WRC streamers to fabric interface
-- "etherbone" = attach Etherbone slave to fabric interface
g_fabric_iface : string := "plain";
g_fabric_iface : string := "plainfbrc";
-- data width when g_fabric_iface = "streamers" (otherwise ignored)
g_streamer_width : integer := 32;
-- memory initialisation file for embedded CPU
......@@ -306,7 +307,7 @@ begin -- architecture struct
g_simulation => g_simulation,
g_with_external_clock_input => f_int2bool(g_with_external_clock_input),
g_pcs_16bit => f_int2bool(g_pcs_16bit),
g_fabric_iface => g_fabric_iface,
g_fabric_iface => f_str2iface_type(g_fabric_iface),
g_streamer_width => g_streamer_width,
g_dpram_initf => g_dpram_initf)
port map (
......
board/vfchd/xwrc_board_vfchd.vhd
View file @ 6f4529b4
This diff is collapsed.
top/spec_ref_design/spec_wr_ref_top.ucf
View file @ 6f4529b4
......@@ -346,4 +346,4 @@ INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
# Force PPS output to always be placed as IOB register
INST "cmp_xwrc_board_spec/cmp_xwr_core/WRPC/PPS_GEN/WRAPPED_PPSGEN/pps_out_o" IOB = FORCE;
INST "cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/PPS_GEN/WRAPPED_PPSGEN/pps_out_o" IOB = FORCE;
top/spec_ref_design/spec_wr_ref_top.vhd
View file @ 6f4529b4
......@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-20
-- Last update: 2017-02-20
-- Last update: 2017-02-22
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the SPEC.
......@@ -53,6 +53,7 @@ use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.wr_board_pkg.all;
use work.wr_spec_pkg.all;
use work.gn4124_core_pkg.all;
......@@ -415,7 +416,7 @@ begin -- architecture top
generic map (
g_simulation => 0,
g_with_external_clock_input => TRUE,
g_fabric_iface => "etherbone")
g_fabric_iface => ETHERBONE)
port map (
areset_n_i => areset_n,
clk_20m_vcxo_i => clk_20m_vcxo_i,
......
top/svec_ref_design/svec_wr_ref_top.ucf
View file @ 6f4529b4
......@@ -368,4 +368,4 @@ NET "rst_n_i" TIG;
NET "vme_sysreset_n_i" TIG;
# Force PPS output to always be placed as IOB register
INST "cmp_xwrc_board_svec/cmp_xwr_core/wrpc/pps_gen/wrapped_ppsgen/pps_out_o" IOB = FORCE;
INST "cmp_xwrc_board_svec/cmp_board_common/cmp_xwr_core/wrpc/pps_gen/wrapped_ppsgen/pps_out_o" IOB = FORCE;
top/svec_ref_design/svec_wr_ref_top.vhd
View file @ 6f4529b4
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-16
-- Last update: 2017-02-20
-- Last update: 2017-02-22
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the SVEC.
......@@ -54,6 +54,7 @@ library work;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.xvme64x_core_pkg.all;
use work.wr_board_pkg.all;
use work.wr_svec_pkg.all;
library unisim;
......@@ -347,7 +348,7 @@ begin -- architecture top
cmp_xwrc_board_svec : xwrc_board_svec
generic map (
g_with_external_clock_input => TRUE,
g_fabric_iface => "etherbone")
g_fabric_iface => ETHERBONE)
port map (
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
......
top/vfchd_ref_design/vfchd_wr_ref_top.vhd
View file @ 6f4529b4
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-01-24
-- Last update: 2017-02-20
-- Last update: 2017-02-22
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the VFC-HD.
......@@ -54,6 +54,7 @@ library work;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.xvme64x_core_pkg.all;
use work.wr_board_pkg.all;
use work.wr_vfchd_pkg.all;
use work.vfchd_i2cmux_pkg.all;
......@@ -395,7 +396,7 @@ begin -- architecture top
cmp_xwrc_board_vfchd : xwrc_board_vfchd
generic map (
g_with_external_clock_input => TRUE,
g_fabric_iface => "etherbone")
g_fabric_iface => ETHERBONE)
port map (
clk_board_125m_i => clk_board_125m_i,
clk_board_20m_i => clk_board_20m_i,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment