board/common: introduce common wrapper for shared features across supported boards

6f4529b4 · Dimitris Lampridis · b01bf0e5 · 6f4529b4 · 6f4529b4 · 6f4529b4
Commit 6f4529b4 authored Feb 22, 2017 by Dimitris Lampridis
20 changed files
--- a/board/common/Manifest.py
+++ b/board/common/Manifest.py
+files = [
+    "wr_board_pkg.vhd",
+    "xwrc_board_common.vhd",
+]
--- a/board/common/wr_board_pkg.vhd
+++ b/board/common/wr_board_pkg.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.wrcore_pkg.all;
+
+package wr_board_pkg is
+
+  type t_board_fabric_iface is (PLAIN, STREAMERS, ETHERBONE, always_last_invalid);
+
+  procedure f_check_fabric_iface_type (
+    constant iface_type : in t_board_fabric_iface);
+
+  function f_str2iface_type (
+    constant iface_str : string)
+    return t_board_fabric_iface;
+
+  component xwrc_board_common is
+    generic (
+      g_simulation                : integer;
+      g_with_external_clock_input : boolean;
+      g_phys_uart                 : boolean;
+      g_virtual_uart              : boolean;
+      g_aux_clks                  : integer;
+      g_ep_rxbuf_size             : integer;
+      g_tx_runt_padding           : boolean;
+      g_dpram_initf               : string;
+      g_dpram_size                : integer;
+      g_interface_mode            : t_wishbone_interface_mode;
+      g_address_granularity       : t_wishbone_address_granularity;
+      g_aux_sdb                   : t_sdb_device;
+      g_softpll_enable_debugger   : boolean;
+      g_vuart_fifo_size           : integer;
+      g_pcs_16bit                 : boolean;
+      g_diag_id                   : integer;
+      g_diag_ver                  : integer;
+      g_diag_ro_size              : integer;
+      g_diag_rw_size              : integer;
+      g_streamer_width            : integer;
+      g_fabric_iface              : t_board_fabric_iface);
+    port (
+      clk_sys_i            : in  std_logic;
+      clk_dmtd_i           : in  std_logic;
+      clk_ref_i            : in  std_logic;
+      clk_aux_i            : in  std_logic_vector(g_aux_clks-1 downto 0)       := (others => '0');
+      clk_ext_i            : in  std_logic                                     := '0';
+      clk_ext_mul_i        : in  std_logic                                     := '0';
+      clk_ext_mul_locked_i : in  std_logic                                     := '1';
+      clk_ext_stopped_i    : in  std_logic                                     := '0';
+      clk_ext_rst_o        : out std_logic;
+      pps_ext_i            : in  std_logic                                     := '0';
+      rst_n_i              : in  std_logic;
+      dac_hpll_load_p1_o   : out std_logic;
+      dac_hpll_data_o      : out std_logic_vector(15 downto 0);
+      dac_dpll_load_p1_o   : out std_logic;
+      dac_dpll_data_o      : out std_logic_vector(15 downto 0);
+      phy8_o               : out t_phy_8bits_from_wrc;
+      phy8_i               : in  t_phy_8bits_to_wrc                            := c_dummy_phy8_to_wrc;
+      phy16_o              : out t_phy_16bits_from_wrc;
+      phy16_i              : in  t_phy_16bits_to_wrc                           := c_dummy_phy16_to_wrc;
+      led_act_o            : out std_logic;
+      led_link_o           : out std_logic;
+      scl_o                : out std_logic;
+      scl_i                : in  std_logic                                     := '1';
+      sda_o                : out std_logic;
+      sda_i                : in  std_logic                                     := '1';
+      sfp_scl_o            : out std_logic;
+      sfp_scl_i            : in  std_logic                                     := '1';
+      sfp_sda_o            : out std_logic;
+      sfp_sda_i            : in  std_logic                                     := '1';
+      sfp_det_i            : in  std_logic;
+      btn1_i               : in  std_logic                                     := '1';
+      btn2_i               : in  std_logic                                     := '1';
+      spi_sclk_o           : out std_logic;
+      spi_ncs_o            : out std_logic;
+      spi_mosi_o           : out std_logic;
+      spi_miso_i           : in  std_logic                                     := '0';
+      uart_rxd_i           : in  std_logic                                     := '0';
+      uart_txd_o           : out std_logic;
+      owr_pwren_o          : out std_logic_vector(1 downto 0);
+      owr_en_o             : out std_logic_vector(1 downto 0);
+      owr_i                : in  std_logic_vector(1 downto 0)                  := (others => '1');
+      slave_i              : in  t_wishbone_slave_in                           := cc_dummy_slave_in;
+      slave_o              : out t_wishbone_slave_out;
+      aux_master_o         : out t_wishbone_master_out;
+      aux_master_i         : in  t_wishbone_master_in                          := cc_dummy_master_in;
+      wrf_src_o            : out t_wrf_source_out;
+      wrf_src_i            : in  t_wrf_source_in                               := c_dummy_src_in;
+      wrf_snk_o            : out t_wrf_sink_out;
+      wrf_snk_i            : in  t_wrf_sink_in                                 := c_dummy_snk_in;
+      wrs_tx_data_i        : in  std_logic_vector(g_streamer_width-1 downto 0) := (others => '0');
+      wrs_tx_valid_i       : in  std_logic                                     := '0';
+      wrs_tx_dreq_o        : out std_logic;
+      wrs_tx_last_i        : in  std_logic                                     := '1';
+      wrs_tx_flush_i       : in  std_logic                                     := '0';
+      wrs_rx_first_o       : out std_logic;
+      wrs_rx_last_o        : out std_logic;
+      wrs_rx_data_o        : out std_logic_vector(g_streamer_width-1 downto 0);
+      wrs_rx_valid_o       : out std_logic;
+      wrs_rx_dreq_i        : in  std_logic                                     := '0';
+      wb_eth_master_o      : out t_wishbone_master_out;
+      wb_eth_master_i      : in  t_wishbone_master_in                          := cc_dummy_master_in;
+      timestamps_o         : out t_txtsu_timestamp;
+      timestamps_ack_i     : in  std_logic                                     := '1';
+      fc_tx_pause_req_i    : in  std_logic                                     := '0';
+      fc_tx_pause_delay_i  : in  std_logic_vector(15 downto 0)                 := x"0000";
+      fc_tx_pause_ready_o  : out std_logic;
+      tm_link_up_o         : out std_logic;
+      tm_dac_value_o       : out std_logic_vector(23 downto 0);
+      tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0);
+      tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0)       := (others => '0');
+      tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0);
+      tm_time_valid_o      : out std_logic;
+      tm_tai_o             : out std_logic_vector(39 downto 0);
+      tm_cycles_o          : out std_logic_vector(27 downto 0);
+      pps_p_o              : out std_logic;
+      pps_led_o            : out std_logic;
+      link_ok_o            : out std_logic);
+  end component xwrc_board_common;
+
+end wr_board_pkg;
+
+package body wr_board_pkg is
+
+  procedure f_check_fabric_iface_type (
+    constant iface_type : in t_board_fabric_iface) is
+  begin
+    if iface_type >= always_last_invalid then
+      assert FALSE
+        report "WR PTP core fabric interface [" & t_board_fabric_iface'image(iface_type) & "] is not supported"
+        severity ERROR;
+    end if;
+  end procedure f_check_fabric_iface_type;
+
+  function f_str2iface_type (
+    constant iface_str : string)
+    return t_board_fabric_iface is
+    variable result : t_board_fabric_iface;
+  begin
+    case iface_str is
+      when "PLAINFBRC" => result := PLAIN;
+      when "STREAMERS" => result := STREAMERS;
+      when "ETHERBONE" => result := ETHERBONE;
+      when others      => result := always_last_invalid;
+    end case;
+    return result;
+  end function f_str2iface_type;
+
+end package body wr_board_pkg;
--- a/board/common/xwrc_board_common.vhd
+++ b/board/common/xwrc_board_common.vhd
+-------------------------------------------------------------------------------
+-- Title      : Common WRPC Wrapper
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : xwrc_board_common.vhd
+-- Author(s)  : Dimitrios Lampridis  <dimitrios.lampridis@cern.ch>
+-- Company    : CERN (BE-CO-HT)
+-- Created    : 2017-02-22
+-- Last update: 2017-02-22
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Wrapper for WR PTP core with common features shared between
+-- the various supported boards. These include the core itself, as well as
+-- a selection of fabric interfaces between the core and the application.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+-------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.wrcore_pkg.all;
+use work.wishbone_pkg.all;
+use work.etherbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.streamers_pkg.all;
+use work.wr_board_pkg.all;
+
+entity xwrc_board_common is
+  generic(
+    g_simulation                : integer                        := 0;
+    g_with_external_clock_input : boolean                        := TRUE;
+    g_phys_uart                 : boolean                        := TRUE;
+    g_virtual_uart              : boolean                        := TRUE;
+    g_aux_clks                  : integer                        := 0;
+    g_ep_rxbuf_size             : integer                        := 1024;
+    g_tx_runt_padding           : boolean                        := TRUE;
+    g_dpram_initf               : string                         := "";
+    g_dpram_size                : integer                        := 131072/4;
+    g_interface_mode            : t_wishbone_interface_mode      := PIPELINED;
+    g_address_granularity       : t_wishbone_address_granularity := BYTE;
+    g_aux_sdb                   : t_sdb_device                   := c_wrc_periph3_sdb;
+    g_softpll_enable_debugger   : boolean                        := FALSE;
+    g_vuart_fifo_size           : integer                        := 1024;
+    g_pcs_16bit                 : boolean                        := FALSE;
+    g_diag_id                   : integer                        := 0;
+    g_diag_ver                  : integer                        := 0;
+    g_diag_ro_size              : integer                        := 0;
+    g_diag_rw_size              : integer                        := 0;
+    g_streamer_width            : integer                        := 32;
+    g_fabric_iface              : t_board_fabric_iface           := PLAIN);
+  port(
+    ---------------------------------------------------------------------------
+    -- Clocks/resets
+    ---------------------------------------------------------------------------
+    -- system reference clock (any frequency <= f(clk_ref_i))
+    clk_sys_i : in std_logic;
+
+    -- DDMTD offset clock (125.x MHz)
+    clk_dmtd_i : in std_logic;
+
+    -- Timing reference (125 MHz)
+    clk_ref_i : in std_logic;
+
+    -- Aux clock (i.e. the FMC clock), which can be disciplined by the WR Core
+    clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+
+    -- External 10 MHz reference (cesium, GPSDO, etc.), used in Grandmaster mode
+    clk_ext_i : in std_logic := '0';
+
+    clk_ext_mul_i        : in  std_logic := '0';
+    clk_ext_mul_locked_i : in  std_logic := '1';
+    clk_ext_stopped_i    : in  std_logic := '0';
+    clk_ext_rst_o        : out std_logic;
+
+    -- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode
+    pps_ext_i : in std_logic := '0';
+
+    rst_n_i : in std_logic;
+
+    ---------------------------------------------------------------------------
+    --Timing system
+    ---------------------------------------------------------------------------
+    dac_hpll_load_p1_o : out std_logic;
+    dac_hpll_data_o    : out std_logic_vector(15 downto 0);
+
+    dac_dpll_load_p1_o : out std_logic;
+    dac_dpll_data_o    : out std_logic_vector(15 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- PHY I/f
+    ---------------------------------------------------------------------------
+    phy8_o  : out t_phy_8bits_from_wrc;
+    phy8_i  : in  t_phy_8bits_to_wrc  := c_dummy_phy8_to_wrc;
+    phy16_o : out t_phy_16bits_from_wrc;
+    phy16_i : in  t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
+
+    ---------------------------------------------------------------------------
+    --GPIO
+    ---------------------------------------------------------------------------
+    led_act_o  : out std_logic;
+    led_link_o : out std_logic;
+    scl_o      : out std_logic;
+    scl_i      : in  std_logic := '1';
+    sda_o      : out std_logic;
+    sda_i      : in  std_logic := '1';
+    sfp_scl_o  : out std_logic;
+    sfp_scl_i  : in  std_logic := '1';
+    sfp_sda_o  : out std_logic;
+    sfp_sda_i  : in  std_logic := '1';
+    sfp_det_i  : in  std_logic;
+    btn1_i     : in  std_logic := '1';
+    btn2_i     : in  std_logic := '1';
+    spi_sclk_o : out std_logic;
+    spi_ncs_o  : out std_logic;
+    spi_mosi_o : out std_logic;
+    spi_miso_i : in  std_logic := '0';
+
+    ---------------------------------------------------------------------------
+    --UART
+    ---------------------------------------------------------------------------
+    uart_rxd_i : in  std_logic := '0';
+    uart_txd_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- 1-wire
+    ---------------------------------------------------------------------------
+    owr_pwren_o : out std_logic_vector(1 downto 0);
+    owr_en_o    : out std_logic_vector(1 downto 0);
+    owr_i       : in  std_logic_vector(1 downto 0) := (others => '1');
+
+    ---------------------------------------------------------------------------
+    --External WB interface
+    ---------------------------------------------------------------------------
+    slave_i : in  t_wishbone_slave_in := cc_dummy_slave_in;
+    slave_o : out t_wishbone_slave_out;
+
+    aux_master_o : out t_wishbone_master_out;
+    aux_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+
+    ---------------------------------------------------------------------------
+    -- External Fabric I/F (when g_fabric_iface = PLAIN)
+    ---------------------------------------------------------------------------
+    wrf_src_o : out t_wrf_source_out;
+    wrf_src_i : in  t_wrf_source_in := c_dummy_src_in;
+    wrf_snk_o : out t_wrf_sink_out;
+    wrf_snk_i : in  t_wrf_sink_in   := c_dummy_snk_in;
+
+    ---------------------------------------------------------------------------
+    -- WR streamers (when g_fabric_iface = STREAMERS)
+    ---------------------------------------------------------------------------
+    wrs_tx_data_i  : in  std_logic_vector(g_streamer_width-1 downto 0) := (others => '0');
+    wrs_tx_valid_i : in  std_logic                                     := '0';
+    wrs_tx_dreq_o  : out std_logic;
+    wrs_tx_last_i  : in  std_logic                                     := '1';
+    wrs_tx_flush_i : in  std_logic                                     := '0';
+    wrs_rx_first_o : out std_logic;
+    wrs_rx_last_o  : out std_logic;
+    wrs_rx_data_o  : out std_logic_vector(g_streamer_width-1 downto 0);
+    wrs_rx_valid_o : out std_logic;
+    wrs_rx_dreq_i  : in  std_logic                                     := '0';
+
+    ---------------------------------------------------------------------------
+    -- Etherbone WB master interface (when g_fabric_iface = ETHERBONE)
+    ---------------------------------------------------------------------------
+    wb_eth_master_o : out t_wishbone_master_out;
+    wb_eth_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+
+    ---------------------------------------------------------------------------
+    -- External Tx Timestamping I/F
+    ---------------------------------------------------------------------------
+    timestamps_o     : out t_txtsu_timestamp;
+    timestamps_ack_i : in  std_logic := '1';
+
+    ---------------------------------------------------------------------------
+    -- Pause Frame Control
+    ---------------------------------------------------------------------------
+    fc_tx_pause_req_i   : in  std_logic                     := '0';
+    fc_tx_pause_delay_i : in  std_logic_vector(15 downto 0) := x"0000";
+    fc_tx_pause_ready_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Timecode/Servo Control
+    ---------------------------------------------------------------------------
+    tm_link_up_o         : out std_logic;
+    -- DAC Control
+    tm_dac_value_o       : out std_logic_vector(23 downto 0);
+    tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0);
+    -- Aux clock lock enable
+    tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+    -- Aux clock locked flag
+    tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0);
+    -- Timecode output
+    tm_time_valid_o      : out std_logic;
+    tm_tai_o             : out std_logic_vector(39 downto 0);
+    tm_cycles_o          : out std_logic_vector(27 downto 0);
+    -- 1PPS output
+    pps_p_o              : out std_logic;
+    pps_led_o            : out std_logic;
+
+    link_ok_o : out std_logic
+    );
+
+end entity xwrc_board_common;
+
+
+architecture struct of xwrc_board_common is
+
+  -----------------------------------------------------------------------------
+  -- Signals
+  -----------------------------------------------------------------------------
+
+  -- Timecode interface
+  signal tm_time_valid : std_logic;
+  signal tm_tai        : std_logic_vector(39 downto 0);
+  signal tm_cycles     : std_logic_vector(27 downto 0);
+
+  -- WR SNMP
+  signal aux_diag_in  : t_generic_word_array(c_WR_TRANS_ARR_SIZE_OUT-1 downto 0);
+  signal aux_diag_out : t_generic_word_array(c_WR_TRANS_ARR_SIZE_IN-1 downto 0);
+
+  -- WR fabric interface
+  signal wrf_src_out : t_wrf_source_out;
+  signal wrf_src_in  : t_wrf_source_in;
+  signal wrf_snk_out : t_wrf_sink_out;
+  signal wrf_snk_in  : t_wrf_sink_in;
+
+  -- Aux WB interface
+  signal aux_master_out : t_wishbone_master_out;
+  signal aux_master_in  : t_wishbone_master_in;
+  signal aux_rst_n      : std_logic;
+
+begin  -- architecture struct
+
+  -- Check for unsupported fabric interface type
+  f_check_fabric_iface_type(g_fabric_iface);
+
+  -----------------------------------------------------------------------------
+  -- The WR PTP core itself
+  -----------------------------------------------------------------------------
+
+  cmp_xwr_core : xwr_core
+    generic map (
+      g_simulation                => g_simulation,
+      g_with_external_clock_input => g_with_external_clock_input,
+      g_phys_uart                 => g_phys_uart,
+      g_virtual_uart              => g_virtual_uart,
+      g_aux_clks                  => g_aux_clks,
+      g_ep_rxbuf_size             => g_ep_rxbuf_size,
+      g_tx_runt_padding           => g_tx_runt_padding,
+      g_dpram_initf               => g_dpram_initf,
+      g_dpram_size                => g_dpram_size,
+      g_interface_mode            => g_interface_mode,
+      g_address_granularity       => g_address_granularity,
+      g_aux_sdb                   => g_aux_sdb,
+      g_softpll_enable_debugger   => g_softpll_enable_debugger,
+      g_vuart_fifo_size           => g_vuart_fifo_size,
+      g_pcs_16bit                 => g_pcs_16bit,
+      g_records_for_phy           => TRUE,
+      g_diag_id                   => g_diag_id,
+      g_diag_ver                  => g_diag_ver,
+      g_diag_ro_size              => g_diag_ro_size,
+      g_diag_rw_size              => g_diag_rw_size)
+    port map (
+      clk_sys_i            => clk_sys_i,
+      clk_dmtd_i           => clk_dmtd_i,
+      clk_ref_i            => clk_ref_i,
+      clk_aux_i            => clk_aux_i,
+      clk_ext_i            => clk_ext_i,
+      clk_ext_mul_i        => clk_ext_mul_i,
+      clk_ext_mul_locked_i => clk_ext_mul_locked_i,
+      clk_ext_stopped_i    => clk_ext_stopped_i,
+      clk_ext_rst_o        => clk_ext_rst_o,
+      pps_ext_i            => pps_ext_i,
+      rst_n_i              => rst_n_i,
+      dac_hpll_load_p1_o   => dac_hpll_load_p1_o,
+      dac_hpll_data_o      => dac_hpll_data_o,
+      dac_dpll_load_p1_o   => dac_dpll_load_p1_o,
+      dac_dpll_data_o      => dac_dpll_data_o,
+      phy_ref_clk_i        => '0',
+      phy_tx_data_o        => open,
+      phy_tx_k_o           => open,
+      phy_tx_disparity_i   => '0',
+      phy_tx_enc_err_i     => '0',
+      phy_rx_data_i        => (others => '0'),
+      phy_rx_rbclk_i       => '0',
+      phy_rx_k_i           => (others => '0'),
+      phy_rx_enc_err_i     => '0',
+      phy_rx_bitslide_i    => (others => '0'),
+      phy_rst_o            => open,
+      phy_rdy_i            => '1',
+      phy_loopen_o         => open,
+      phy_loopen_vec_o     => open,
+      phy_tx_prbs_sel_o    => open,
+      phy_sfp_tx_fault_i   => '0',
+      phy_sfp_los_i        => '0',
+      phy_sfp_tx_disable_o => open,
+      phy8_o               => phy8_o,
+      phy8_i               => phy8_i,
+      phy16_o              => phy16_o,
+      phy16_i              => phy16_i,
+      led_act_o            => led_act_o,
+      led_link_o           => led_link_o,
+      scl_o                => scl_o,
+      scl_i                => scl_i,
+      sda_o                => sda_o,
+      sda_i                => sda_i,
+      sfp_scl_o            => sfp_scl_o,
+      sfp_scl_i            => sfp_scl_i,
+      sfp_sda_o            => sfp_sda_o,
+      sfp_sda_i            => sfp_sda_i,
+      sfp_det_i            => sfp_det_i,
+      btn1_i               => btn1_i,
+      btn2_i               => btn2_i,
+      spi_sclk_o           => spi_sclk_o,
+      spi_ncs_o            => spi_ncs_o,
+      spi_mosi_o           => spi_mosi_o,
+      spi_miso_i           => spi_miso_i,
+      uart_rxd_i           => uart_rxd_i,
+      uart_txd_o           => uart_txd_o,
+      owr_pwren_o          => owr_pwren_o,
+      owr_en_o             => owr_en_o,
+      owr_i                => owr_i,
+      slave_i              => slave_i,
+      slave_o              => slave_o,
+      aux_master_o         => aux_master_out,
+      aux_master_i         => aux_master_in,
+      wrf_src_o            => wrf_src_out,
+      wrf_src_i            => wrf_src_in,
+      wrf_snk_o            => wrf_snk_out,
+      wrf_snk_i            => wrf_snk_in,
+      timestamps_o         => timestamps_o,
+      timestamps_ack_i     => timestamps_ack_i,
+      fc_tx_pause_req_i    => fc_tx_pause_req_i,
+      fc_tx_pause_delay_i  => fc_tx_pause_delay_i,
+      fc_tx_pause_ready_o  => fc_tx_pause_ready_o,
+      tm_link_up_o         => tm_link_up_o,
+      tm_dac_value_o       => tm_dac_value_o,
+      tm_dac_wr_o          => tm_dac_wr_o,
+      tm_clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
+      tm_clk_aux_locked_o  => tm_clk_aux_locked_o,
+      tm_time_valid_o      => tm_time_valid,
+      tm_tai_o             => tm_tai,
+      tm_cycles_o          => tm_cycles,
+      pps_p_o              => pps_p_o,
+      pps_led_o            => pps_led_o,
+      rst_aux_n_o          => aux_rst_n,
+      aux_diag_i           => aux_diag_in,
+      aux_diag_o           => aux_diag_out,
+      link_ok_o            => link_ok_o);
+
+  tm_time_valid_o <= tm_time_valid;
+  tm_tai_o        <= tm_tai;
+  tm_cycles_o     <= tm_cycles;
+
+  gen_wr_streamers : if (g_fabric_iface = STREAMERS) generate
+
+    cmp_xwr_transmission : xwr_transmission
+      generic map (
+        g_tx_data_width => g_streamer_width,
+        g_rx_data_width => g_streamer_width)
+      port map (
+        clk_sys_i       => clk_sys_i,
+        rst_n_i         => rst_n_i,
+        src_i           => wrf_snk_out,
+        src_o           => wrf_snk_in,
+        snk_i           => wrf_src_out,
+        snk_o           => wrf_src_in,
+        tx_data_i       => wrs_tx_data_i,
+        tx_valid_i      => wrs_tx_valid_i,
+        tx_dreq_o       => wrs_tx_dreq_o,
+        tx_last_p1_i    => wrs_tx_last_i,
+        tx_flush_p1_i   => wrs_tx_flush_i,
+        rx_first_p1_o   => wrs_rx_first_o,
+        rx_last_p1_o    => wrs_rx_last_o,
+        rx_data_o       => wrs_rx_data_o,
+        rx_valid_o      => wrs_rx_valid_o,
+        rx_dreq_i       => wrs_rx_dreq_i,
+        clk_ref_i       => clk_ref_i,
+        tm_time_valid_i => tm_time_valid,
+        tm_tai_i        => tm_tai,
+        tm_cycles_i     => tm_cycles,
+        wb_slave_i      => aux_master_out,
+        wb_slave_o      => aux_master_in,
+        snmp_array_o    => aux_diag_in,
+        snmp_array_i    => aux_diag_out);
+
+    -- unused output ports
+    wrf_src_o <= c_dummy_snk_in;
+    wrf_snk_o <= c_dummy_src_in;
+
+    aux_master_o    <= cc_dummy_master_out;
+    wb_eth_master_o <= cc_dummy_master_out;
+
+  end generate gen_wr_streamers;
+
+  gen_etherbone : if (g_fabric_iface = ETHERBONE) generate
+
+    cmp_eb_ethernet_slave : eb_ethernet_slave
+      generic map (
+        g_sdb_address => x"0000000000030000")
+      port map (
+        clk_i       => clk_sys_i,
+        nRst_i      => aux_rst_n,
+        src_o       => wrf_snk_in,
+        src_i       => wrf_snk_out,
+        snk_o       => wrf_src_in,
+        snk_i       => wrf_src_out,
+        cfg_slave_o => aux_master_in,
+        cfg_slave_i => aux_master_out,
+        master_o    => wb_eth_master_o,
+        master_i    => wb_eth_master_i);
+
+    -- unused output ports
+    wrf_src_o <= c_dummy_snk_in;
+    wrf_snk_o <= c_dummy_src_in;
+
+    wrs_tx_dreq_o  <= '0';
+    wrs_rx_first_o <= '0';
+    wrs_rx_last_o  <= '0';
+    wrs_rx_valid_o <= '0';
+    wrs_rx_data_o  <= (others => '0');
+
+    aux_master_o <= cc_dummy_master_out;
+
+    -- unused inputs to WR PTP core
+    aux_diag_in <= (others => (others => '0'));
+
+  end generate gen_etherbone;
+
+  gen_wr_fabric : if (g_fabric_iface = PLAIN) generate
+
+    wrf_src_o <= wrf_src_out;
+    wrf_snk_o <= wrf_snk_out;
+
+    wrf_src_in <= wrf_src_i;
+    wrf_snk_in <= wrf_snk_i;
+
+    -- unused output ports
+    wrs_tx_dreq_o  <= '0';
+    wrs_rx_first_o <= '0';
+    wrs_rx_last_o  <= '0';
+    wrs_rx_valid_o <= '0';
+    wrs_rx_data_o  <= (others => '0');
+
+    wb_eth_master_o <= cc_dummy_master_out;
+
+    aux_master_in <= aux_master_i;
+    aux_master_o  <= aux_master_out;
+
+    -- unused inputs to WR PTP core
+    aux_diag_in <= (others => (others => '0'));
+
+  end generate gen_wr_fabric;
+
+end architecture struct;
--- a/board/spec/Manifest.py
+++ b/board/spec/Manifest.py
@@ -3,3 +3,9 @@ files = [
    "xwrc_board_spec.vhd",
    "wrc_board_spec.vhd",
 ]
+
+modules = {
+    "local" : [
+        "../common",
+    ]
+}
--- a/board/spec/wr_spec_pkg.vhd
+++ b/board/spec/wr_spec_pkg.vhd
@@ -4,16 +4,17 @@ use ieee.std_logic_1164.all;
 library work;
 use work.wishbone_pkg.all;
 use work.wr_fabric_pkg.all;
+use work.wr_board_pkg.all;

 package wr_spec_pkg is

  component xwrc_board_spec is
    generic (
-      g_simulation                : integer := 0;
-      g_with_external_clock_input : boolean := TRUE;
-      g_fabric_iface              : string  := "plainfbrc";
-      g_streamer_width            : integer := 32;
-      g_dpram_initf               : string  := "../../bin/wrpc/wrc_phy8.bram");
+      g_simulation                : integer              := 0;
+      g_with_external_clock_input : boolean              := TRUE;
+      g_fabric_iface              : t_board_fabric_iface := PLAIN;
+      g_streamer_width            : integer              := 32;
+      g_dpram_initf               : string               := "../../bin/wrpc/wrc_phy8.bram");
    port (
      areset_n_i          : in  std_logic;
      clk_20m_vcxo_i      : in  std_logic;
@@ -21,7 +22,7 @@ package wr_spec_pkg is
      clk_125m_pllref_n_i : in  std_logic;
      clk_125m_gtp_n_i    : in  std_logic;
      clk_125m_gtp_p_i    : in  std_logic;
-      clk_10m_ext_ref_i   : in  std_logic  := '0';
+      clk_10m_ext_ref_i   : in  std_logic                                     := '0';
      clk_sys_62m5_o      : out std_logic;
      clk_ref_125m_o      : out std_logic;
      rst_62m5_n_o        : out std_logic;
@@ -34,15 +35,15 @@ package wr_spec_pkg is
      sfp_txn_o           : out std_logic;
      sfp_rxp_i           : in  std_logic;
      sfp_rxn_i           : in  std_logic;
-      sfp_det_i           : in  std_logic  := '1';
+      sfp_det_i           : in  std_logic                                     := '1';
      sfp_sda_i           : in  std_logic;
      sfp_sda_o           : out std_logic;
      sfp_scl_i           : in  std_logic;
      sfp_scl_o           : out std_logic;
      sfp_rate_select_o   : out std_logic;
-      sfp_tx_fault_i      : in  std_logic  := '0';
+      sfp_tx_fault_i      : in  std_logic                                     := '0';
      sfp_tx_disable_o    : out std_logic;
-      sfp_los_i           : in  std_logic  := '0';
+      sfp_los_i           : in  std_logic                                     := '0';
      eeprom_sda_i        : in  std_logic;
      eeprom_sda_o        : out std_logic;
      eeprom_scl_i        : in  std_logic;
@@ -62,15 +63,15 @@ package wr_spec_pkg is
      wrf_snk_o           : out t_wrf_sink_out;
      wrf_snk_i           : in  t_wrf_sink_in                                 := c_dummy_snk_in;
      wrs_tx_data_i       : in  std_logic_vector(g_streamer_width-1 downto 0) := (others => '0');
-      wrs_tx_valid_i      : in  std_logic  := '0';
+      wrs_tx_valid_i      : in  std_logic                                     := '0';
      wrs_tx_dreq_o       : out std_logic;
-      wrs_tx_last_i       : in  std_logic  := '1';
-      wrs_tx_flush_i      : in  std_logic  := '0';
+      wrs_tx_last_i       : in  std_logic                                     := '1';
+      wrs_tx_flush_i      : in  std_logic                                     := '0';
      wrs_rx_first_o      : out std_logic;
      wrs_rx_last_o       : out std_logic;
      wrs_rx_data_o       : out std_logic_vector(g_streamer_width-1 downto 0);
      wrs_rx_valid_o      : out std_logic;
-      wrs_rx_dreq_i       : in  std_logic  := '0';
+      wrs_rx_dreq_i       : in  std_logic                                     := '0';
      wb_eth_master_o     : out t_wishbone_master_out;
      wb_eth_master_i     : in  t_wishbone_master_in                          := cc_dummy_master_in;
      pps_ext_i           : in  std_logic;
@@ -87,7 +88,7 @@ package wr_spec_pkg is
    generic (
      g_simulation                : integer := 0;
      g_with_external_clock_input : integer := 1;
-      g_fabric_iface              : string  := "plain";
+      g_fabric_iface              : string  := "PLAINFBRC";
      g_streamer_width            : integer := 32;
      g_dpram_initf               : string  := "../../bin/wrpc/wrc_phy8.bram");
    port (
@@ -97,7 +98,7 @@ package wr_spec_pkg is
      clk_125m_pllref_n_i : in  std_logic;
      clk_125m_gtp_n_i    : in  std_logic;
      clk_125m_gtp_p_i    : in  std_logic;
-      clk_10m_ext_ref_i   : in  std_logic  := '0';
+      clk_10m_ext_ref_i   : in  std_logic                                               := '0';
      clk_sys_62m5_o      : out std_logic;
      clk_ref_125m_o      : out std_logic;
      rst_62m5_n_o        : out std_logic;
@@ -110,15 +111,15 @@ package wr_spec_pkg is
      sfp_txn_o           : out std_logic;
      sfp_rxp_i           : in  std_logic;
      sfp_rxn_i           : in  std_logic;
-      sfp_det_i           : in  std_logic  := '1';
+      sfp_det_i           : in  std_logic                                               := '1';
      sfp_sda_i           : in  std_logic;
      sfp_sda_o           : out std_logic;
      sfp_scl_i           : in  std_logic;
      sfp_scl_o           : out std_logic;
      sfp_rate_select_o   : out std_logic;
-      sfp_tx_fault_i      : in  std_logic  := '0';
+      sfp_tx_fault_i      : in  std_logic                                               := '0';
      sfp_tx_disable_o    : out std_logic;
-      sfp_los_i           : in  std_logic  := '0';
+      sfp_los_i           : in  std_logic                                               := '0';
      eeprom_sda_i        : in  std_logic;
      eeprom_sda_o        : out std_logic;
      eeprom_scl_i        : in  std_logic;
@@ -135,9 +136,9 @@ package wr_spec_pkg is
      wb_dat_i            : in  std_logic_vector(c_wishbone_data_width-1 downto 0)      := (others => '0');
      wb_dat_o            : out std_logic_vector(c_wishbone_data_width-1 downto 0);
      wb_sel_i            : in  std_logic_vector(c_wishbone_address_width/8-1 downto 0) := (others => '0');
-      wb_we_i             : in  std_logic  := '0';
-      wb_cyc_i            : in  std_logic  := '0';
-      wb_stb_i            : in  std_logic  := '0';
+      wb_we_i             : in  std_logic                                               := '0';
+      wb_cyc_i            : in  std_logic                                               := '0';
+      wb_stb_i            : in  std_logic                                               := '0';
      wb_ack_o            : out std_logic;
      wb_int_o            : out std_logic;
      wb_err_o            : out std_logic;
@@ -164,15 +165,15 @@ package wr_spec_pkg is
      wrf_snk_err_o       : out std_logic;
      wrf_snk_rty_o       : out std_logic;
      wrs_tx_data_i       : in  std_logic_vector(g_streamer_width-1 downto 0)           := (others => '0');
-      wrs_tx_valid_i      : in  std_logic  := '0';
+      wrs_tx_valid_i      : in  std_logic                                               := '0';
      wrs_tx_dreq_o       : out std_logic;
-      wrs_tx_last_i       : in  std_logic  := '1';
-      wrs_tx_flush_i      : in  std_logic  := '0';
+      wrs_tx_last_i       : in  std_logic                                               := '1';
+      wrs_tx_flush_i      : in  std_logic                                               := '0';
      wrs_rx_first_o      : out std_logic;
      wrs_rx_last_o       : out std_logic;
      wrs_rx_data_o       : out std_logic_vector(g_streamer_width-1 downto 0);
      wrs_rx_valid_o      : out std_logic;
-      wrs_rx_dreq_i       : in  std_logic  := '0';
+      wrs_rx_dreq_i       : in  std_logic                                               := '0';
      wb_eth_adr_o        : out std_logic_vector(c_wishbone_address_width-1 downto 0);
      wb_eth_dat_o        : out std_logic_vector(c_wishbone_data_width-1 downto 0);
      wb_eth_dat_i        : in  std_logic_vector(c_wishbone_data_width-1 downto 0)      := (others => '0');
@@ -180,11 +181,11 @@ package wr_spec_pkg is
      wb_eth_we_o         : out std_logic;
      wb_eth_cyc_o        : out std_logic;
      wb_eth_stb_o        : out std_logic;
-      wb_eth_ack_i        : in  std_logic  := '0';
-      wb_eth_int_i        : in  std_logic  := '0';
-      wb_eth_err_i        : in  std_logic  := '0';
-      wb_eth_rty_i        : in  std_logic  := '0';
-      wb_eth_stall_i      : in  std_logic  := '0';
+      wb_eth_ack_i        : in  std_logic                                               := '0';
+      wb_eth_int_i        : in  std_logic                                               := '0';
+      wb_eth_err_i        : in  std_logic                                               := '0';
+      wb_eth_rty_i        : in  std_logic                                               := '0';
+      wb_eth_stall_i      : in  std_logic                                               := '0';
      pps_ext_i           : in  std_logic;
      pps_p_o             : out std_logic;
      pps_led_o           : out std_logic;

--- a/board/spec/wrc_board_spec.vhd
+++ b/board/spec/wrc_board_spec.vhd
@@ -7,7 +7,7 @@
 -- Author(s)  : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2016-02-17
-- Last update: 2017-02-17
+-- Last update: 2017-02-22
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
 -- Description: Top-level wrapper for WR PTP core including all the modules
@@ -50,6 +50,7 @@ use work.wr_fabric_pkg.all;
 use work.endpoint_pkg.all;
 use work.streamers_pkg.all;
 use work.wr_xilinx_pkg.all;
+use work.wr_board_pkg.all;
 use work.wr_spec_pkg.all;

 entity wrc_board_spec is
@@ -58,10 +59,10 @@ entity wrc_board_spec is
    g_simulation                : integer := 0;
    -- Select whether to include external ref clock input
    g_with_external_clock_input : integer := 1;
-    -- "plain" = expose WRC fabric interface
+    -- "plainfbrc" = expose WRC fabric interface
    -- "streamers" = attach WRC streamers to fabric interface
    -- "etherbone" = attach Etherbone slave to fabric interface
-    g_fabric_iface              : string  := "plain";
+    g_fabric_iface              : string  := "plainfbrc";
    -- data width when g_fabric_iface = "streamers" (otherwise ignored)
    g_streamer_width            : integer := 32;
    -- memory initialisation file for embedded CPU
@@ -325,7 +326,7 @@ begin  -- architecture struct
    generic map (
      g_simulation                => g_simulation,
      g_with_external_clock_input => f_int2bool(g_with_external_clock_input),
-      g_fabric_iface              => g_fabric_iface,
+      g_fabric_iface              => f_str2iface_type(g_fabric_iface),
      g_streamer_width            => g_streamer_width,
      g_dpram_initf               => g_dpram_initf)
    port map (

--- a/board/spec/xwrc_board_spec.vhd
+++ b/board/spec/xwrc_board_spec.vhd
@@ -7,7 +7,7 @@
 -- Author(s)  : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2017-02-17
-- Last update: 2017-02-17
+-- Last update: 2017-02-22
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
 -- Description: Top-level wrapper for WR PTP core including all the modules
@@ -48,6 +48,7 @@ use work.wr_fabric_pkg.all;
 use work.endpoint_pkg.all;
 use work.streamers_pkg.all;
 use work.wr_xilinx_pkg.all;
+use work.wr_board_pkg.all;
 use work.wr_spec_pkg.all;

 library unisim;
@@ -56,17 +57,17 @@ use unisim.vcomponents.all;
 entity xwrc_board_spec is
  generic(
    -- set to 1 to speed up some initialization processes during simulation
-    g_simulation                : integer := 0;
+    g_simulation                : integer              := 0;
    -- Select whether to include external ref clock input
-    g_with_external_clock_input : boolean := TRUE;
-    -- "plainfbrc" = expose WRC fabric interface
-    -- "streamers" = attach WRC streamers to fabric interface
-    -- "etherbone" = attach Etherbone slave to fabric interface
-    g_fabric_iface              : string  := "plainfbrc";
+    g_with_external_clock_input : boolean              := TRUE;
+    -- plain     = expose WRC fabric interface
+    -- streamers = attach WRC streamers to fabric interface
+    -- etherbone = attach Etherbone slave to fabric interface
+    g_fabric_iface              : t_board_fabric_iface := plain;
    -- data width when g_fabric_iface = "streamers" (otherwise ignored)
-    g_streamer_width            : integer := 32;
+    g_streamer_width            : integer              := 32;
    -- memory initialisation file for embedded CPU
-    g_dpram_initf               : string  := "../../bin/wrpc/wrc_phy8.bram"
+    g_dpram_initf               : string               := "../../bin/wrpc/wrc_phy8.bram"
    );
  port (
    ---------------------------------------------------------------------------
@@ -244,28 +245,8 @@ architecture struct of xwrc_board_spec is
  signal onewire_en : std_logic_vector(1 downto 0);

  -- PHY
-  signal phy8_to_wrc    : t_phy_8bits_to_wrc;
-  signal phy8_from_wrc  : t_phy_8bits_from_wrc;
-
-  -- Timecode interface
-  signal tm_time_valid : std_logic;
-  signal tm_tai        : std_logic_vector(39 downto 0);
-  signal tm_cycles     : std_logic_vector(27 downto 0);
-
-  -- WR SNMP
-  signal aux_diag_in  : t_generic_word_array(c_WR_TRANS_ARR_SIZE_OUT-1 downto 0);
-  signal aux_diag_out : t_generic_word_array(c_WR_TRANS_ARR_SIZE_IN-1 downto 0);
-
-  -- WR fabric interface
-  signal wrf_src_out : t_wrf_source_out;
-  signal wrf_src_in  : t_wrf_source_in;
-  signal wrf_snk_out : t_wrf_sink_out;
-  signal wrf_snk_in  : t_wrf_sink_in;
-
-  -- Aux WB interface
-  signal aux_master_out : t_wishbone_master_out;
-  signal aux_master_in  : t_wishbone_master_in;
-  signal aux_rst_n      : std_logic;
+  signal phy8_to_wrc   : t_phy_8bits_to_wrc;
+  signal phy8_from_wrc : t_phy_8bits_from_wrc;

  -- External reference
  signal ext_ref_mul         : std_logic;
@@ -273,40 +254,8 @@ architecture struct of xwrc_board_spec is
  signal ext_ref_mul_stopped : std_logic;
  signal ext_ref_rst         : std_logic;

-
-  component spec_serial_dac is
-    generic (
-      g_num_data_bits  : integer;
-      g_num_extra_bits : integer;
-      g_num_cs_select  : integer);
-    port (
-      clk_i         : in  std_logic;
-      rst_n_i       : in  std_logic;
-      value_i       : in  std_logic_vector(g_num_data_bits-1 downto 0);
-      cs_sel_i      : in  std_logic_vector(g_num_cs_select-1 downto 0);
-      load_i        : in  std_logic;
-      sclk_divsel_i : in  std_logic_vector(2 downto 0);
-      dac_cs_n_o    : out std_logic_vector(g_num_cs_select-1 downto 0);
-      dac_sclk_o    : out std_logic;
-      dac_sdata_o   : out std_logic;
-      xdone_o       : out std_logic);
-  end component spec_serial_dac;
-
 begin  -- architecture struct

-  -----------------------------------------------------------------------------
-  -- Check for unsupported features and/or misconfiguration
-  -----------------------------------------------------------------------------
-
-  gen_unknown_wrfabric : if(g_fabric_iface /= "plainfbrc") and
-                           (g_fabric_iface /= "streamers") and
-                           (g_fabric_iface /= "etherbone")
-  generate
-    assert FALSE
-      report "WR PTP core fabric interface [" & g_fabric_iface & "] is not supported"
-      severity ERROR;
-  end generate gen_unknown_wrfabric;
-
  -----------------------------------------------------------------------------
  -- Platform-dependent part (PHY, PLLs, buffers, etc)
  -----------------------------------------------------------------------------
@@ -388,9 +337,9 @@ begin  -- architecture struct
  -- 2x SPI DAC
  -----------------------------------------------------------------------------

-  cmp_dac_arb: spec_serial_dac_arb
+  cmp_dac_arb : spec_serial_dac_arb
    generic map (
-      g_invert_sclk    => false,
+      g_invert_sclk    => FALSE,
      g_num_extra_bits => 8)
    port map (
      clk_i         => clk_pll_62m5,
@@ -405,10 +354,10 @@ begin  -- architecture struct
      dac_din_o     => plldac_din_o);

  -----------------------------------------------------------------------------
-  -- The WR PTP core itself
+  -- The WR PTP core with optional fabric interface attached
  -----------------------------------------------------------------------------

-  cmp_xwr_core : xwr_core
+  cmp_board_common : xwrc_board_common
    generic map (
      g_simulation                => g_simulation,
      g_with_external_clock_input => TRUE,
@@ -425,11 +374,12 @@ begin  -- architecture struct
      g_softpll_enable_debugger   => FALSE,
      g_vuart_fifo_size           => 1024,
      g_pcs_16bit                 => FALSE,
-      g_records_for_phy           => TRUE,
      g_diag_id                   => 0,
      g_diag_ver                  => 0,
      g_diag_ro_size              => c_WR_TRANS_ARR_SIZE_OUT,
-      g_diag_rw_size              => c_WR_TRANS_ARR_SIZE_IN
+      g_diag_rw_size              => c_WR_TRANS_ARR_SIZE_IN,
+      g_streamer_width            => g_streamer_width,
+      g_fabric_iface              => g_fabric_iface
      )
    port map (
      clk_sys_i            => clk_pll_62m5,
@@ -473,12 +423,22 @@ begin  -- architecture struct
      owr_i                => onewire_in,
      slave_i              => wb_slave_i,
      slave_o              => wb_slave_o,
-      aux_master_o         => aux_master_out,
-      aux_master_i         => aux_master_in,
-      wrf_src_o            => wrf_src_out,
-      wrf_src_i            => wrf_src_in,
-      wrf_snk_o            => wrf_snk_out,
-      wrf_snk_i            => wrf_snk_in,
+      wrf_src_o            => wrf_src_o,
+      wrf_src_i            => wrf_src_i,
+      wrf_snk_o            => wrf_snk_o,
+      wrf_snk_i            => wrf_snk_i,
+      wrs_tx_data_i        => wrs_tx_data_i,
+      wrs_tx_valid_i       => wrs_tx_valid_i,
+      wrs_tx_dreq_o        => wrs_tx_dreq_o,
+      wrs_tx_last_i        => wrs_tx_last_i,
+      wrs_tx_flush_i       => wrs_tx_flush_i,
+      wrs_rx_first_o       => wrs_rx_first_o,
+      wrs_rx_last_o        => wrs_rx_last_o,
+      wrs_rx_data_o        => wrs_rx_data_o,
+      wrs_rx_valid_o       => wrs_rx_valid_o,
+      wrs_rx_dreq_i        => wrs_rx_dreq_i,
+      wb_eth_master_o      => wb_eth_master_o,
+      wb_eth_master_i      => wb_eth_master_i,
      timestamps_o         => open,
      timestamps_ack_i     => '1',
      fc_tx_pause_req_i    => '0',
@@ -489,14 +449,11 @@ begin  -- architecture struct
      tm_dac_wr_o          => open,
      tm_clk_aux_lock_en_i => (others => '0'),
      tm_clk_aux_locked_o  => open,
-      tm_time_valid_o      => tm_time_valid,
-      tm_tai_o             => tm_tai,
-      tm_cycles_o          => tm_cycles,
+      tm_time_valid_o      => tm_time_valid_o,
+      tm_tai_o             => tm_tai_o,
+      tm_cycles_o          => tm_cycles_o,
      pps_p_o              => pps_p_o,
      pps_led_o            => pps_led_o,
-      rst_aux_n_o          => aux_rst_n,
-      aux_diag_i           => aux_diag_in,
-      aux_diag_o           => aux_diag_out,
      link_ok_o            => open);

  sfp_rate_select_o <= '1';
@@ -505,103 +462,4 @@ begin  -- architecture struct
  onewire_in(0) <= onewire_i;
  onewire_in(1) <= '1';

-  tm_time_valid_o <= tm_time_valid;
-  tm_tai_o        <= tm_tai;
-  tm_cycles_o     <= tm_cycles;
-
-  gen_wr_streamers : if (g_fabric_iface = "streamers") generate
-
-    cmp_xwr_transmission : xwr_transmission
-      generic map (
-        g_tx_data_width => g_streamer_width,
-        g_rx_data_width => g_streamer_width)
-      port map (
-        clk_sys_i       => clk_pll_62m5,
-        rst_n_i         => rst_62m5_n,
-        src_i           => wrf_snk_out,
-        src_o           => wrf_snk_in,
-        snk_i           => wrf_src_out,
-        snk_o           => wrf_src_in,
-        tx_data_i       => wrs_tx_data_i,
-        tx_valid_i      => wrs_tx_valid_i,
-        tx_dreq_o       => wrs_tx_dreq_o,
-        tx_last_p1_i    => wrs_tx_last_i,
-        tx_flush_p1_i   => wrs_tx_flush_i,
-        rx_first_p1_o   => wrs_rx_first_o,
-        rx_last_p1_o    => wrs_rx_last_o,
-        rx_data_o       => wrs_rx_data_o,
-        rx_valid_o      => wrs_rx_valid_o,
-        rx_dreq_i       => wrs_rx_dreq_i,
-        clk_ref_i       => clk_pll_125m,
-        tm_time_valid_i => tm_time_valid,
-        tm_tai_i        => tm_tai,
-        tm_cycles_i     => tm_cycles,
-        wb_slave_i      => aux_master_out,
-        wb_slave_o      => aux_master_in,
-        snmp_array_o    => aux_diag_in,
-        snmp_array_i    => aux_diag_out);
-
-    -- unused output ports
-    wrf_src_o <= c_dummy_snk_in;
-    wrf_snk_o <= c_dummy_src_in;
-
-    wb_eth_master_o <= cc_dummy_master_out;
-
-  end generate gen_wr_streamers;
-
-  gen_etherbone : if (g_fabric_iface = "etherbone") generate
-
-    cmp_eb_ethernet_slave : eb_ethernet_slave
-      generic map (
-        g_sdb_address => x"0000000000030000")
-      port map (
-        clk_i       => clk_pll_62m5,
-        nRst_i      => aux_rst_n,
-        src_o       => wrf_snk_in,
-        src_i       => wrf_snk_out,
-        snk_o       => wrf_src_in,
-        snk_i       => wrf_src_out,
-        cfg_slave_o => aux_master_in,
-        cfg_slave_i => aux_master_out,
-        master_o    => wb_eth_master_o,
-        master_i    => wb_eth_master_i);
-
-    -- unused output ports
-    wrf_src_o <= c_dummy_snk_in;
-    wrf_snk_o <= c_dummy_src_in;
-
-    wrs_tx_dreq_o  <= '0';
-    wrs_rx_first_o <= '0';
-    wrs_rx_last_o  <= '0';
-    wrs_rx_valid_o <= '0';
-    wrs_rx_data_o  <= (others => '0');
-
-    -- unused inputs to WR PTP core
-    aux_diag_in <= (others => (others => '0'));
-
-  end generate gen_etherbone;
-
-  gen_wr_fabric : if (g_fabric_iface = "plainfbrc") generate
-
-    wrf_src_o <= wrf_src_out;
-    wrf_snk_o <= wrf_snk_out;
-
-    wrf_src_in <= wrf_src_i;
-    wrf_snk_in <= wrf_snk_i;
-
-    -- unused output ports
-    wrs_tx_dreq_o  <= '0';
-    wrs_rx_first_o <= '0';
-    wrs_rx_last_o  <= '0';
-    wrs_rx_valid_o <= '0';
-    wrs_rx_data_o  <= (others => '0');
-
-    wb_eth_master_o <= cc_dummy_master_out;
-
-    -- unused inputs to WR PTP core
-    aux_diag_in   <= (others => (others => '0'));
-    aux_master_in <= cc_dummy_master_in;
-
-  end generate gen_wr_fabric;
-
 end architecture struct;
--- a/board/svec/Manifest.py
+++ b/board/svec/Manifest.py
@@ -3,3 +3,9 @@ files = [
    "xwrc_board_svec.vhd",
    "wrc_board_svec.vhd",
 ]
+
+modules = {
+    "local" : [
+        "../common",
+    ]
+}
--- a/board/svec/wr_svec_pkg.vhd
+++ b/board/svec/wr_svec_pkg.vhd
@@ -4,16 +4,17 @@ use ieee.std_logic_1164.all;
 library work;
 use work.wishbone_pkg.all;
 use work.wr_fabric_pkg.all;
+use work.wr_board_pkg.all;

 package wr_svec_pkg is

  component xwrc_board_svec is
    generic (
-      g_simulation                : integer := 0;
-      g_with_external_clock_input : boolean := TRUE;
-      g_fabric_iface              : string  := "plainfbrc";
-      g_streamer_width            : integer := 32;
-      g_dpram_initf               : string  := "../../bin/wrpc/wrc_phy8.bram");
+      g_simulation                : integer              := 0;
+      g_with_external_clock_input : boolean              := TRUE;
+      g_fabric_iface              : t_board_fabric_iface := PLAIN;
+      g_streamer_width            : integer              := 32;
+      g_dpram_initf               : string               := "../../bin/wrpc/wrc_phy8.bram");
    port (
      areset_n_i          : in  std_logic;
      clk_20m_vcxo_i      : in  std_logic;
@@ -88,7 +89,7 @@ package wr_svec_pkg is
    generic (
      g_simulation                : integer := 0;
      g_with_external_clock_input : integer := 1;
-      g_fabric_iface              : string  := "plain";
+      g_fabric_iface              : string  := "PLAINFBRC";
      g_streamer_width            : integer := 32;
      g_dpram_initf               : string  := "../../bin/wrpc/wrc_phy8.bram");
    port (

--- a/board/svec/wrc_board_svec.vhd
+++ b/board/svec/wrc_board_svec.vhd
@@ -7,7 +7,7 @@
 -- Author(s)  : Dimitrios Lampridis  <dimitrios.lampridis@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2016-02-16
-- Last update: 2017-02-20
+-- Last update: 2017-02-22
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
 -- Description: Top-level wrapper for WR PTP core including all the modules
@@ -50,6 +50,7 @@ use work.wr_fabric_pkg.all;
 use work.endpoint_pkg.all;
 use work.streamers_pkg.all;
 use work.wr_xilinx_pkg.all;
+use work.wr_board_pkg.all;
 use work.wr_svec_pkg.all;

 entity wrc_board_svec is
@@ -58,10 +59,10 @@ entity wrc_board_svec is
    g_simulation                : integer := 0;
    -- Select whether to include external ref clock input
    g_with_external_clock_input : integer := 1;
-    -- "plain" = expose WRC fabric interface
+    -- "plainfbrc" = expose WRC fabric interface
    -- "streamers" = attach WRC streamers to fabric interface
    -- "etherbone" = attach Etherbone slave to fabric interface
-    g_fabric_iface              : string  := "plain";
+    g_fabric_iface              : string  := "plainfbrc";
    -- data width when g_fabric_iface = "streamers" (otherwise ignored)
    g_streamer_width            : integer := 32;
    -- memory initialisation file for embedded CPU
@@ -327,7 +328,7 @@ begin  -- architecture struct
    generic map (
      g_simulation                => g_simulation,
      g_with_external_clock_input => f_int2bool(g_with_external_clock_input),
-      g_fabric_iface              => g_fabric_iface,
+      g_fabric_iface              => f_str2iface_type(g_fabric_iface),
      g_streamer_width            => g_streamer_width,
      g_dpram_initf               => g_dpram_initf)
    port map (

--- a/board/svec/xwrc_board_svec.vhd
+++ b/board/svec/xwrc_board_svec.vhd
@@ -48,6 +48,7 @@ use work.wr_fabric_pkg.all;
 use work.endpoint_pkg.all;
 use work.streamers_pkg.all;
 use work.wr_xilinx_pkg.all;
+use work.wr_board_pkg.all;
 use work.wr_svec_pkg.all;

 library unisim;
@@ -56,17 +57,17 @@ use unisim.vcomponents.all;
 entity xwrc_board_svec is
  generic(
    -- set to 1 to speed up some initialization processes during simulation
-    g_simulation                : integer := 0;
+    g_simulation                : integer              := 0;
    -- Select whether to include external ref clock input
-    g_with_external_clock_input : boolean := TRUE;
-    -- "plainfbrc" = expose WRC fabric interface
-    -- "streamers" = attach WRC streamers to fabric interface
-    -- "etherbone" = attach Etherbone slave to fabric interface
-    g_fabric_iface              : string  := "plainfbrc";
+    g_with_external_clock_input : boolean              := TRUE;
+    -- plain     = expose WRC fabric interface
+    -- streamers = attach WRC streamers to fabric interface
+    -- etherbone = attach Etherbone slave to fabric interface
+    g_fabric_iface              : t_board_fabric_iface := plain;
    -- data width when g_fabric_iface = "streamers" (otherwise ignored)
-    g_streamer_width            : integer := 32;
+    g_streamer_width            : integer              := 32;
    -- memory initialisation file for embedded CPU
-    g_dpram_initf               : string  := "../../bin/wrpc/wrc_phy8.bram"
+    g_dpram_initf               : string               := "../../bin/wrpc/wrc_phy8.bram"
    );
  port (
    ---------------------------------------------------------------------------
@@ -236,6 +237,9 @@ architecture struct of xwrc_board_svec is
  signal rstlogic_rst_out : std_logic_vector(0 downto 0);

  -- PLL DAC ARB
+  signal dac_sync_n       : std_logic_vector(1 downto 0);
+  signal dac_sclk         : std_logic;
+  signal dac_din          : std_logic;
  signal dac_hpll_load_p1 : std_logic;
  signal dac_hpll_data    : std_logic_vector(15 downto 0);
  signal dac_dpll_load_p1 : std_logic;
@@ -251,66 +255,14 @@ architecture struct of xwrc_board_svec is
  signal phy16_to_wrc   : t_phy_16bits_to_wrc;
  signal phy16_from_wrc : t_phy_16bits_from_wrc;

-  -- Timecode interface
-  signal tm_time_valid : std_logic;
-  signal tm_tai        : std_logic_vector(39 downto 0);
-  signal tm_cycles     : std_logic_vector(27 downto 0);
-
-  -- WR SNMP
-  signal aux_diag_in  : t_generic_word_array(c_WR_TRANS_ARR_SIZE_OUT-1 downto 0);
-  signal aux_diag_out : t_generic_word_array(c_WR_TRANS_ARR_SIZE_IN-1 downto 0);
-
-  -- WR fabric interface
-  signal wrf_src_out : t_wrf_source_out;
-  signal wrf_src_in  : t_wrf_source_in;
-  signal wrf_snk_out : t_wrf_sink_out;
-  signal wrf_snk_in  : t_wrf_sink_in;
-
-  -- Aux WB interface
-  signal aux_master_out : t_wishbone_master_out;
-  signal aux_master_in  : t_wishbone_master_in;
-  signal aux_rst_n      : std_logic;
-
  -- External reference
  signal ext_ref_mul         : std_logic;
  signal ext_ref_mul_locked  : std_logic;
  signal ext_ref_mul_stopped : std_logic;
  signal ext_ref_rst         : std_logic;

-
-  component spec_serial_dac is
-    generic (
-      g_num_data_bits  : integer;
-      g_num_extra_bits : integer;
-      g_num_cs_select  : integer);
-    port (
-      clk_i         : in  std_logic;
-      rst_n_i       : in  std_logic;
-      value_i       : in  std_logic_vector(g_num_data_bits-1 downto 0);
-      cs_sel_i      : in  std_logic_vector(g_num_cs_select-1 downto 0);
-      load_i        : in  std_logic;
-      sclk_divsel_i : in  std_logic_vector(2 downto 0);
-      dac_cs_n_o    : out std_logic_vector(g_num_cs_select-1 downto 0);
-      dac_sclk_o    : out std_logic;
-      dac_sdata_o   : out std_logic;
-      xdone_o       : out std_logic);
-  end component spec_serial_dac;
-
 begin  -- architecture struct

-  -----------------------------------------------------------------------------
-  -- Check for unsupported features and/or misconfiguration
-  -----------------------------------------------------------------------------
-
-  gen_unknown_wrfabric : if(g_fabric_iface /= "plainfbrc") and
-                           (g_fabric_iface /= "streamers") and
-                           (g_fabric_iface /= "etherbone")
-  generate
-    assert FALSE
-      report "WR PTP core fabric interface [" & g_fabric_iface & "] is not supported"
-      severity ERROR;
-  end generate gen_unknown_wrfabric;
-
  -----------------------------------------------------------------------------
  -- Platform-dependent part (PHY, PLLs, buffers, etc)
  -----------------------------------------------------------------------------
@@ -392,45 +344,33 @@ begin  -- architecture struct
  -- 2x SPI DAC
  -----------------------------------------------------------------------------

-  cmp_dac_helper : spec_serial_dac
+  cmp_dac_arb : spec_serial_dac_arb
    generic map (
-      g_num_data_bits  => 16,
-      g_num_extra_bits => 8,
-      g_num_cs_select  => 1)
+      g_invert_sclk    => FALSE,
+      g_num_extra_bits => 8)
    port map (
-      clk_i         => clk_pll_62m5,
-      rst_n_i       => rst_62m5_n,
-      value_i       => dac_hpll_data,
-      cs_sel_i      => "1",
-      load_i        => dac_hpll_load_p1,
-      sclk_divsel_i => "010",
-      dac_cs_n_o(0) => pll20dac_sync_n_o,
-      dac_sclk_o    => pll20dac_sclk_o,
-      dac_sdata_o   => pll20dac_din_o,
-      xdone_o       => open);
-
-  cmp_dac_main : spec_serial_dac
-    generic map (
-      g_num_data_bits  => 16,
-      g_num_extra_bits => 8,
-      g_num_cs_select  => 1)
-    port map (
-      clk_i         => clk_pll_62m5,
-      rst_n_i       => rst_62m5_n,
-      value_i       => dac_dpll_data,
-      cs_sel_i      => "1",
-      load_i        => dac_dpll_load_p1,
-      sclk_divsel_i => "010",
-      dac_cs_n_o(0) => pll25dac_sync_n_o,
-      dac_sclk_o    => pll25dac_sclk_o,
-      dac_sdata_o   => pll25dac_din_o,
-      xdone_o       => open);
+      clk_i      => clk_pll_62m5,
+      rst_n_i    => rst_62m5_n,
+      val1_i     => dac_dpll_data,
+      load1_i    => dac_dpll_load_p1,
+      val2_i     => dac_hpll_data,
+      load2_i    => dac_hpll_load_p1,
+      dac_cs_n_o => dac_sync_n,
+      dac_sclk_o => dac_sclk,
+      dac_din_o  => dac_din);
+
+  pll20dac_din_o    <= dac_din;
+  pll20dac_sclk_o   <= dac_sclk;
+  pll20dac_sync_n_o <= dac_sync_n(1);
+  pll25dac_din_o    <= dac_din;
+  pll25dac_sclk_o   <= dac_sclk;
+  pll25dac_sync_n_o <= dac_sync_n(0);

  -----------------------------------------------------------------------------
-  -- The WR PTP core itself
+  -- The WR PTP core with optional fabric interface attached
  -----------------------------------------------------------------------------

-  cmp_xwr_core : xwr_core
+  cmp_board_common : xwrc_board_common
    generic map (
      g_simulation                => g_simulation,
      g_with_external_clock_input => TRUE,
@@ -447,11 +387,12 @@ begin  -- architecture struct
      g_softpll_enable_debugger   => FALSE,
      g_vuart_fifo_size           => 1024,
      g_pcs_16bit                 => FALSE,
-      g_records_for_phy           => TRUE,
      g_diag_id                   => 0,
      g_diag_ver                  => 0,
      g_diag_ro_size              => c_WR_TRANS_ARR_SIZE_OUT,
-      g_diag_rw_size              => c_WR_TRANS_ARR_SIZE_IN
+      g_diag_rw_size              => c_WR_TRANS_ARR_SIZE_IN,
+      g_streamer_width            => g_streamer_width,
+      g_fabric_iface              => g_fabric_iface
      )
    port map (
      clk_sys_i            => clk_pll_62m5,
@@ -497,12 +438,22 @@ begin  -- architecture struct
      owr_i                => onewire_in,
      slave_i              => wb_slave_i,
      slave_o              => wb_slave_o,
-      aux_master_o         => aux_master_out,
-      aux_master_i         => aux_master_in,
-      wrf_src_o            => wrf_src_out,
-      wrf_src_i            => wrf_src_in,
-      wrf_snk_o            => wrf_snk_out,
-      wrf_snk_i            => wrf_snk_in,
+      wrf_src_o            => wrf_src_o,
+      wrf_src_i            => wrf_src_i,
+      wrf_snk_o            => wrf_snk_o,
+      wrf_snk_i            => wrf_snk_i,
+      wrs_tx_data_i        => wrs_tx_data_i,
+      wrs_tx_valid_i       => wrs_tx_valid_i,
+      wrs_tx_dreq_o        => wrs_tx_dreq_o,
+      wrs_tx_last_i        => wrs_tx_last_i,
+      wrs_tx_flush_i       => wrs_tx_flush_i,
+      wrs_rx_first_o       => wrs_rx_first_o,
+      wrs_rx_last_o        => wrs_rx_last_o,
+      wrs_rx_data_o        => wrs_rx_data_o,
+      wrs_rx_valid_o       => wrs_rx_valid_o,
+      wrs_rx_dreq_i        => wrs_rx_dreq_i,
+      wb_eth_master_o      => wb_eth_master_o,
+      wb_eth_master_i      => wb_eth_master_i,
      timestamps_o         => open,
      timestamps_ack_i     => '1',
      fc_tx_pause_req_i    => '0',
@@ -513,14 +464,11 @@ begin  -- architecture struct
      tm_dac_wr_o          => open,
      tm_clk_aux_lock_en_i => (others => '0'),
      tm_clk_aux_locked_o  => open,
-      tm_time_valid_o      => tm_time_valid,
-      tm_tai_o             => tm_tai,
-      tm_cycles_o          => tm_cycles,
+      tm_time_valid_o      => tm_time_valid_o,
+      tm_tai_o             => tm_tai_o,
+      tm_cycles_o          => tm_cycles_o,
      pps_p_o              => pps_p_o,
      pps_led_o            => pps_led_o,
-      rst_aux_n_o          => aux_rst_n,
-      aux_diag_i           => aux_diag_in,
-      aux_diag_o           => aux_diag_out,
      link_ok_o            => open);

  sfp_rate_select_o <= '1';
@@ -529,103 +477,4 @@ begin  -- architecture struct
  onewire_in(0) <= onewire_i;
  onewire_in(1) <= '1';

-  tm_time_valid_o <= tm_time_valid;
-  tm_tai_o        <= tm_tai;
-  tm_cycles_o     <= tm_cycles;
-
-  gen_wr_streamers : if (g_fabric_iface = "streamers") generate
-
-    cmp_xwr_transmission : xwr_transmission
-      generic map (
-        g_tx_data_width => g_streamer_width,
-        g_rx_data_width => g_streamer_width)
-      port map (
-        clk_sys_i       => clk_pll_62m5,
-        rst_n_i         => rst_62m5_n,
-        src_i           => wrf_snk_out,
-        src_o           => wrf_snk_in,
-        snk_i           => wrf_src_out,
-        snk_o           => wrf_src_in,
-        tx_data_i       => wrs_tx_data_i,
-        tx_valid_i      => wrs_tx_valid_i,
-        tx_dreq_o       => wrs_tx_dreq_o,
-        tx_last_p1_i    => wrs_tx_last_i,
-        tx_flush_p1_i   => wrs_tx_flush_i,
-        rx_first_p1_o   => wrs_rx_first_o,
-        rx_last_p1_o    => wrs_rx_last_o,
-        rx_data_o       => wrs_rx_data_o,
-        rx_valid_o      => wrs_rx_valid_o,
-        rx_dreq_i       => wrs_rx_dreq_i,
-        clk_ref_i       => clk_pll_125m,
-        tm_time_valid_i => tm_time_valid,
-        tm_tai_i        => tm_tai,
-        tm_cycles_i     => tm_cycles,
-        wb_slave_i      => aux_master_out,
-        wb_slave_o      => aux_master_in,
-        snmp_array_o    => aux_diag_in,
-        snmp_array_i    => aux_diag_out);
-
-    -- unused output ports
-    wrf_src_o <= c_dummy_snk_in;
-    wrf_snk_o <= c_dummy_src_in;
-
-    wb_eth_master_o <= cc_dummy_master_out;
-
-  end generate gen_wr_streamers;
-
-  gen_etherbone : if (g_fabric_iface = "etherbone") generate
-
-    cmp_eb_ethernet_slave : eb_ethernet_slave
-      generic map (
-        g_sdb_address => x"0000000000030000")
-      port map (
-        clk_i       => clk_pll_62m5,
-        nRst_i      => aux_rst_n,
-        src_o       => wrf_snk_in,
-        src_i       => wrf_snk_out,
-        snk_o       => wrf_src_in,
-        snk_i       => wrf_src_out,
-        cfg_slave_o => aux_master_in,
-        cfg_slave_i => aux_master_out,
-        master_o    => wb_eth_master_o,
-        master_i    => wb_eth_master_i);
-
-    -- unused output ports
-    wrf_src_o <= c_dummy_snk_in;
-    wrf_snk_o <= c_dummy_src_in;
-
-    wrs_tx_dreq_o  <= '0';
-    wrs_rx_first_o <= '0';
-    wrs_rx_last_o  <= '0';
-    wrs_rx_valid_o <= '0';
-    wrs_rx_data_o  <= (others => '0');
-
-    -- unused inputs to WR PTP core
-    aux_diag_in <= (others => (others => '0'));
-
-  end generate gen_etherbone;
-
-  gen_wr_fabric : if (g_fabric_iface = "plainfbrc") generate
-
-    wrf_src_o <= wrf_src_out;
-    wrf_snk_o <= wrf_snk_out;
-
-    wrf_src_in <= wrf_src_i;
-    wrf_snk_in <= wrf_snk_i;
-
-    -- unused output ports
-    wrs_tx_dreq_o  <= '0';
-    wrs_rx_first_o <= '0';
-    wrs_rx_last_o  <= '0';
-    wrs_rx_valid_o <= '0';
-    wrs_rx_data_o  <= (others => '0');
-
-    wb_eth_master_o <= cc_dummy_master_out;
-
-    -- unused inputs to WR PTP core
-    aux_diag_in   <= (others => (others => '0'));
-    aux_master_in <= cc_dummy_master_in;
-
-  end generate gen_wr_fabric;
-
 end architecture struct;
--- a/board/vfchd/Manifest.py
+++ b/board/vfchd/Manifest.py
@@ -4,3 +4,9 @@ files = [
    "wrc_board_vfchd.vhd",
    "sfp_i2c_adapter.vhd",
 ]
+
+modules = {
+    "local" : [
+        "../common",
+    ]
+}
--- a/board/vfchd/wr_vfchd_pkg.vhd
+++ b/board/vfchd/wr_vfchd_pkg.vhd
@@ -4,17 +4,18 @@ use ieee.std_logic_1164.all;
 library work;
 use work.wishbone_pkg.all;
 use work.wr_fabric_pkg.all;
+use work.wr_board_pkg.all;

 package wr_vfchd_pkg is

  component xwrc_board_vfchd is
    generic (
-      g_simulation                : integer := 0;
-      g_with_external_clock_input : boolean := TRUE;
-      g_pcs_16bit                 : boolean := FALSE;
-      g_fabric_iface              : string  := "plain";
-      g_streamer_width            : integer := 32;
-      g_dpram_initf               : string  := "../../bin/wrpc/wrc_phy8.mif");
+      g_simulation                : integer              := 0;
+      g_with_external_clock_input : boolean              := TRUE;
+      g_pcs_16bit                 : boolean              := FALSE;
+      g_fabric_iface              : t_board_fabric_iface := PLAIN;
+      g_streamer_width            : integer              := 32;
+      g_dpram_initf               : string               := "../../bin/wrpc/wrc_phy8.mif");
    port (
      clk_board_125m_i  : in  std_logic;
      clk_board_20m_i   : in  std_logic;
@@ -73,7 +74,7 @@ package wr_vfchd_pkg is
      g_simulation                : integer := 0;
      g_with_external_clock_input : integer := 1;
      g_pcs_16bit                 : integer := 0;
-      g_fabric_iface              : string  := "plain";
+      g_fabric_iface              : string  := "PLAINFBRC";
      g_streamer_width            : integer := 32;
      g_dpram_initf               : string  := "../../bin/wrpc/wrc_phy8.mif");
    port (

--- a/board/vfchd/wrc_board_vfchd.vhd
+++ b/board/vfchd/wrc_board_vfchd.vhd
@@ -7,7 +7,7 @@
 -- Author(s)  : Dimitrios Lampridis  <dimitrios.lampridis@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2016-07-26
-- Last update: 2017-02-20
+-- Last update: 2017-02-22
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
 -- Description: Top-level wrapper for WR PTP core including all the modules
@@ -50,6 +50,7 @@ use work.wr_fabric_pkg.all;
 use work.endpoint_pkg.all;
 use work.streamers_pkg.all;
 use work.wr_altera_pkg.all;
+use work.wr_board_pkg.all;
 use work.wr_vfchd_pkg.all;

 entity wrc_board_vfchd is
@@ -60,10 +61,10 @@ entity wrc_board_vfchd is
    g_with_external_clock_input : integer := 1;
    -- set to 1 to use 16bit PCS (instead of default 8bit PCS)
    g_pcs_16bit                 : integer := 0;
-    -- "plain"     = expose WRC fabric interface
+    -- "plainfbrc" = expose WRC fabric interface
    -- "streamers" = attach WRC streamers to fabric interface
    -- "etherbone" = attach Etherbone slave to fabric interface
-    g_fabric_iface              : string  := "plain";
+    g_fabric_iface              : string  := "plainfbrc";
    -- data width when g_fabric_iface = "streamers" (otherwise ignored)
    g_streamer_width            : integer := 32;
    -- memory initialisation file for embedded CPU
@@ -306,7 +307,7 @@ begin  -- architecture struct
      g_simulation                => g_simulation,
      g_with_external_clock_input => f_int2bool(g_with_external_clock_input),
      g_pcs_16bit                 => f_int2bool(g_pcs_16bit),
-      g_fabric_iface              => g_fabric_iface,
+      g_fabric_iface              => f_str2iface_type(g_fabric_iface),
      g_streamer_width            => g_streamer_width,
      g_dpram_initf               => g_dpram_initf)
    port map (

--- a/board/vfchd/xwrc_board_vfchd.vhd
+++ b/board/vfchd/xwrc_board_vfchd.vhd
@@ -48,24 +48,25 @@ use work.wr_fabric_pkg.all;
 use work.endpoint_pkg.all;
 use work.streamers_pkg.all;
 use work.wr_altera_pkg.all;
+use work.wr_board_pkg.all;
 use work.wr_vfchd_pkg.all;

 entity xwrc_board_vfchd is
  generic(
    -- set to 1 to speed up some initialization processes during simulation
-    g_simulation                : integer := 0;
+    g_simulation                : integer              := 0;
    -- Select whether to include external ref clock input
-    g_with_external_clock_input : boolean := TRUE;
+    g_with_external_clock_input : boolean              := TRUE;
    -- set to TRUE to use 16bit PCS (instead of default 8bit PCS)
-    g_pcs_16bit                 : boolean := FALSE;
-    -- "plain"     = expose WRC fabric interface
-    -- "streamers" = attach WRC streamers to fabric interface
-    -- "etherbone" = attach Etherbone slave to fabric interface
-    g_fabric_iface              : string  := "plain";
+    g_pcs_16bit                 : boolean              := FALSE;
+    -- plain     = expose WRC fabric interface
+    -- streamers = attach WRC streamers to fabric interface
+    -- etherbone = attach Etherbone slave to fabric interface
+    g_fabric_iface              : t_board_fabric_iface := plain;
    -- data width when g_fabric_iface = "streamers" (otherwise ignored)
-    g_streamer_width            : integer := 32;
+    g_streamer_width            : integer              := 32;
    -- memory initialisation file for embedded CPU
-    g_dpram_initf               : string  := "../../bin/wrpc/wrc_phy8.mif"
+    g_dpram_initf               : string               := "../../bin/wrpc/wrc_phy8.mif"
    );
  port (
    ---------------------------------------------------------------------------
@@ -230,26 +231,6 @@ architecture struct of xwrc_board_vfchd is
  signal sfp_i2c_sda_in : std_logic;
  signal sfp_i2c_sda_en : std_logic;

-  -- Timecode interface
-  signal tm_time_valid : std_logic;
-  signal tm_tai        : std_logic_vector(39 downto 0);
-  signal tm_cycles     : std_logic_vector(27 downto 0);
-
-  -- WR SNMP
-  signal aux_diag_in  : t_generic_word_array(c_WR_TRANS_ARR_SIZE_OUT-1 downto 0);
-  signal aux_diag_out : t_generic_word_array(c_WR_TRANS_ARR_SIZE_IN-1 downto 0);
-
-  -- WR fabric interface
-  signal wrf_src_out : t_wrf_source_out;
-  signal wrf_src_in  : t_wrf_source_in;
-  signal wrf_snk_out : t_wrf_sink_out;
-  signal wrf_snk_in  : t_wrf_sink_in;
-
-  -- Aux WB interface
-  signal aux_master_out : t_wishbone_master_out;
-  signal aux_master_in  : t_wishbone_master_in;
-  signal aux_rst_n      : std_logic;
-
  -- External reference
  signal ext_ref_mul        : std_logic;
  signal ext_ref_mul_locked : std_logic;
@@ -258,19 +239,6 @@ architecture struct of xwrc_board_vfchd is

 begin  -- architecture struct

-  -----------------------------------------------------------------------------
-  -- Check for unsupported features and/or misconfiguration
-  -----------------------------------------------------------------------------
-
-  gen_unknown_wrfabric : if(g_fabric_iface /= "plain") and
-                           (g_fabric_iface /= "streamers") and
-                           (g_fabric_iface /= "etherbone")
-  generate
-    assert FALSE
-      report "WR PTP core fabric interface [" & g_fabric_iface & "] is not supported"
-      severity ERROR;
-  end generate gen_unknown_wrfabric;
-
  -----------------------------------------------------------------------------
  -- Platform-dependent part (PHY, PLLs, etc)
  -----------------------------------------------------------------------------
@@ -295,7 +263,7 @@ begin  -- architecture struct
      clk_125m_ref_o       => clk_pll_125m,
      clk_62m5_dmtd_o      => clk_pll_dmtd,
      pll_locked_o         => pll_locked,
-      clk_10m_ext_o         => clk_10m_ext,
+      clk_10m_ext_o        => clk_10m_ext,
      phy8_o               => phy8_to_wrc,
      phy8_i               => phy8_from_wrc,
      phy16_o              => phy16_to_wrc,
@@ -378,10 +346,10 @@ begin  -- architecture struct
      sfp_data_i      => sfp_data_i);

  -----------------------------------------------------------------------------
-  -- The WR PTP core itself
+  -- The WR PTP core with optional fabric interface attached
  -----------------------------------------------------------------------------

-  cmp_xwr_core : xwr_core
+  cmp_board_common : xwrc_board_common
    generic map (
      g_simulation                => g_simulation,
      -- temporary, does not work without it (gui produces periodic message:
@@ -401,11 +369,12 @@ begin  -- architecture struct
      g_softpll_enable_debugger   => FALSE,
      g_vuart_fifo_size           => 1024,
      g_pcs_16bit                 => g_pcs_16bit,
-      g_records_for_phy           => TRUE,
      g_diag_id                   => 0,
      g_diag_ver                  => 0,
      g_diag_ro_size              => c_WR_TRANS_ARR_SIZE_OUT,
-      g_diag_rw_size              => c_WR_TRANS_ARR_SIZE_IN
+      g_diag_rw_size              => c_WR_TRANS_ARR_SIZE_IN,
+      g_streamer_width            => g_streamer_width,
+      g_fabric_iface              => g_fabric_iface
      )
    port map (
      clk_sys_i            => clk_pll_62m5,
@@ -451,12 +420,22 @@ begin  -- architecture struct
      owr_i                => onewire_in,
      slave_i              => wb_slave_i,
      slave_o              => wb_slave_o,
-      aux_master_o         => aux_master_out,
-      aux_master_i         => aux_master_in,
-      wrf_src_o            => wrf_src_out,
-      wrf_src_i            => wrf_src_in,
-      wrf_snk_o            => wrf_snk_out,
-      wrf_snk_i            => wrf_snk_in,
+      wrf_src_o            => wrf_src_o,
+      wrf_src_i            => wrf_src_i,
+      wrf_snk_o            => wrf_snk_o,
+      wrf_snk_i            => wrf_snk_i,
+      wrs_tx_data_i        => wrs_tx_data_i,
+      wrs_tx_valid_i       => wrs_tx_valid_i,
+      wrs_tx_dreq_o        => wrs_tx_dreq_o,
+      wrs_tx_last_i        => wrs_tx_last_i,
+      wrs_tx_flush_i       => wrs_tx_flush_i,
+      wrs_rx_first_o       => wrs_rx_first_o,
+      wrs_rx_last_o        => wrs_rx_last_o,
+      wrs_rx_data_o        => wrs_rx_data_o,
+      wrs_rx_valid_o       => wrs_rx_valid_o,
+      wrs_rx_dreq_i        => wrs_rx_dreq_i,
+      wb_eth_master_o      => wb_eth_master_o,
+      wb_eth_master_i      => wb_eth_master_i,
      timestamps_o         => open,
      timestamps_ack_i     => '1',
      fc_tx_pause_req_i    => '0',
@@ -467,113 +446,11 @@ begin  -- architecture struct
      tm_dac_wr_o          => open,
      tm_clk_aux_lock_en_i => (others => '0'),
      tm_clk_aux_locked_o  => open,
-      tm_time_valid_o      => tm_time_valid,
-      tm_tai_o             => tm_tai,
-      tm_cycles_o          => tm_cycles,
+      tm_time_valid_o      => tm_time_valid_o,
+      tm_tai_o             => tm_tai_o,
+      tm_cycles_o          => tm_cycles_o,
      pps_p_o              => pps_p_o,
      pps_led_o            => pps_led_o,
-      rst_aux_n_o          => aux_rst_n,
-      aux_diag_i           => aux_diag_in,
-      aux_diag_o           => aux_diag_out,
      link_ok_o            => open);

-  tm_time_valid_o <= tm_time_valid;
-  tm_tai_o        <= tm_tai;
-  tm_cycles_o     <= tm_cycles;
-
-  gen_wr_streamers : if (g_fabric_iface = "streamers") generate
-
-    cmp_xwr_transmission : xwr_transmission
-      generic map (
-        g_tx_data_width => g_streamer_width,
-        g_rx_data_width => g_streamer_width)
-      port map (
-        clk_sys_i       => clk_pll_62m5,
-        rst_n_i         => rst_62m5_n,
-        src_i           => wrf_snk_out,
-        src_o           => wrf_snk_in,
-        snk_i           => wrf_src_out,
-        snk_o           => wrf_src_in,
-        tx_data_i       => wrs_tx_data_i,
-        tx_valid_i      => wrs_tx_valid_i,
-        tx_dreq_o       => wrs_tx_dreq_o,
-        tx_last_p1_i    => wrs_tx_last_i,
-        tx_flush_p1_i   => wrs_tx_flush_i,
-        rx_first_p1_o   => wrs_rx_first_o,
-        rx_last_p1_o    => wrs_rx_last_o,
-        rx_data_o       => wrs_rx_data_o,
-        rx_valid_o      => wrs_rx_valid_o,
-        rx_dreq_i       => wrs_rx_dreq_i,
-        clk_ref_i       => clk_pll_125m,
-        tm_time_valid_i => tm_time_valid,
-        tm_tai_i        => tm_tai,
-        tm_cycles_i     => tm_cycles,
-        wb_slave_i      => aux_master_out,
-        wb_slave_o      => aux_master_in,
-        snmp_array_o    => aux_diag_in,
-        snmp_array_i    => aux_diag_out);
-
-    -- unused output ports
-    wrf_src_o <= c_dummy_snk_in;
-    wrf_snk_o <= c_dummy_src_in;
-
-    wb_eth_master_o <= cc_dummy_master_out;
-
-  end generate gen_wr_streamers;
-
-  gen_etherbone : if (g_fabric_iface = "etherbone") generate
-
-    cmp_eb_ethernet_slave : eb_ethernet_slave
-      generic map (
-        g_sdb_address => x"0000000000030000")
-      port map (
-        clk_i       => clk_pll_62m5,
-        nRst_i      => aux_rst_n,
-        src_o       => wrf_snk_in,
-        src_i       => wrf_snk_out,
-        snk_o       => wrf_src_in,
-        snk_i       => wrf_src_out,
-        cfg_slave_o => aux_master_in,
-        cfg_slave_i => aux_master_out,
-        master_o    => wb_eth_master_o,
-        master_i    => wb_eth_master_i);
-
-    -- unused output ports
-    wrf_src_o <= c_dummy_snk_in;
-    wrf_snk_o <= c_dummy_src_in;
-
-    wrs_tx_dreq_o  <= '0';
-    wrs_rx_first_o <= '0';
-    wrs_rx_last_o  <= '0';
-    wrs_rx_valid_o <= '0';
-    wrs_rx_data_o  <= (others => '0');
-
-    -- unused inputs to WR PTP core
-    aux_diag_in <= (others => (others => '0'));
-
-  end generate gen_etherbone;
-
-  gen_wr_fabric : if (g_fabric_iface = "plain") generate
-
-    wrf_src_o <= wrf_src_out;
-    wrf_snk_o <= wrf_snk_out;
-
-    wrf_src_in <= wrf_src_i;
-    wrf_snk_in <= wrf_snk_i;
-
-    -- unused output ports
-    wrs_tx_dreq_o  <= '0';
-    wrs_rx_first_o <= '0';
-    wrs_rx_last_o  <= '0';
-    wrs_rx_valid_o <= '0';
-    wrs_rx_data_o  <= (others => '0');
-
-    wb_eth_master_o <= cc_dummy_master_out;
-
-    -- unused inputs to WR PTP core
-    aux_diag_in   <= (others => (others => '0'));
-    aux_master_in <= cc_dummy_master_in;
-
-  end generate gen_wr_fabric;
-
 end architecture struct;
--- a/top/spec_ref_design/spec_wr_ref_top.ucf
+++ b/top/spec_ref_design/spec_wr_ref_top.ucf
@@ -346,4 +346,4 @@ INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
 TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;

 # Force PPS output to always be placed as IOB register
-INST "cmp_xwrc_board_spec/cmp_xwr_core/WRPC/PPS_GEN/WRAPPED_PPSGEN/pps_out_o" IOB = FORCE;
+INST "cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/PPS_GEN/WRAPPED_PPSGEN/pps_out_o" IOB = FORCE;
--- a/top/spec_ref_design/spec_wr_ref_top.vhd
+++ b/top/spec_ref_design/spec_wr_ref_top.vhd
@@ -7,7 +7,7 @@
 -- Author(s)  : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2017-02-20
-- Last update: 2017-02-20
+-- Last update: 2017-02-22
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
 -- Description: Top-level file for the WRPC reference design on the SPEC.
@@ -53,6 +53,7 @@ use ieee.numeric_std.all;
 library work;
 use work.gencores_pkg.all;
 use work.wishbone_pkg.all;
+use work.wr_board_pkg.all;
 use work.wr_spec_pkg.all;
 use work.gn4124_core_pkg.all;

@@ -415,7 +416,7 @@ begin  -- architecture top
    generic map (
      g_simulation                => 0,
      g_with_external_clock_input => TRUE,
-      g_fabric_iface              => "etherbone")
+      g_fabric_iface              => ETHERBONE)
    port map (
      areset_n_i          => areset_n,
      clk_20m_vcxo_i      => clk_20m_vcxo_i,

--- a/top/svec_ref_design/svec_wr_ref_top.ucf
+++ b/top/svec_ref_design/svec_wr_ref_top.ucf
@@ -368,4 +368,4 @@ NET "rst_n_i" TIG;
 NET "vme_sysreset_n_i" TIG;

 # Force PPS output to always be placed as IOB register
-INST "cmp_xwrc_board_svec/cmp_xwr_core/wrpc/pps_gen/wrapped_ppsgen/pps_out_o" IOB = FORCE;
+INST "cmp_xwrc_board_svec/cmp_board_common/cmp_xwr_core/wrpc/pps_gen/wrapped_ppsgen/pps_out_o" IOB = FORCE;
--- a/top/svec_ref_design/svec_wr_ref_top.vhd
+++ b/top/svec_ref_design/svec_wr_ref_top.vhd
@@ -7,7 +7,7 @@
 -- Author(s)  : Dimitrios Lampridis  <dimitrios.lampridis@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2017-02-16
-- Last update: 2017-02-20
+-- Last update: 2017-02-22
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
 -- Description: Top-level file for the WRPC reference design on the SVEC.
@@ -54,6 +54,7 @@ library work;
 use work.gencores_pkg.all;
 use work.wishbone_pkg.all;
 use work.xvme64x_core_pkg.all;
+use work.wr_board_pkg.all;
 use work.wr_svec_pkg.all;

 library unisim;
@@ -347,7 +348,7 @@ begin  -- architecture top
  cmp_xwrc_board_svec : xwrc_board_svec
    generic map (
      g_with_external_clock_input => TRUE,
-      g_fabric_iface              => "etherbone")
+      g_fabric_iface              => ETHERBONE)
    port map (
      clk_20m_vcxo_i      => clk_20m_vcxo_i,
      clk_125m_pllref_p_i => clk_125m_pllref_p_i,

--- a/top/vfchd_ref_design/vfchd_wr_ref_top.vhd
+++ b/top/vfchd_ref_design/vfchd_wr_ref_top.vhd
@@ -7,7 +7,7 @@
 -- Author(s)  : Dimitrios Lampridis  <dimitrios.lampridis@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2017-01-24
-- Last update: 2017-02-20
+-- Last update: 2017-02-22
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
 -- Description: Top-level file for the WRPC reference design on the VFC-HD.
@@ -54,6 +54,7 @@ library work;
 use work.gencores_pkg.all;
 use work.wishbone_pkg.all;
 use work.xvme64x_core_pkg.all;
+use work.wr_board_pkg.all;
 use work.wr_vfchd_pkg.all;
 use work.vfchd_i2cmux_pkg.all;

@@ -395,7 +396,7 @@ begin  -- architecture top
  cmp_xwrc_board_vfchd : xwrc_board_vfchd
    generic map (
      g_with_external_clock_input => TRUE,
-      g_fabric_iface              => "etherbone")
+      g_fabric_iface              => ETHERBONE)
    port map (
      clk_board_125m_i  => clk_board_125m_i,
      clk_board_20m_i   => clk_board_20m_i,