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White Rabbit core collection
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5fd68a1c
Commit
5fd68a1c
authored
Jul 28, 2016
by
Maciej Lipinski
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Plain Diff
[wr transmission] added wb access for sniffing b-field in tx/rx
parent
7ab89921
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4 changed files
with
50 additions
and
7 deletions
+50
-7
wr_transmission_wb.vhd
wr_transmission_wb.vhd
+15
-1
wr_transmission_wb.wb
wr_transmission_wb.wb
+22
-0
wr_transmission_wbgen2_pkg.vhd
wr_transmission_wbgen2_pkg.vhd
+7
-1
xwr_transmission.vhd
xwr_transmission.vhd
+6
-5
No files found.
wr_transmission_wb.vhd
View file @
5fd68a1c
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wr_transmission_wb.vhd
-- Author : auto-generated by wbgen2 from wr_transmission_wb.wb
-- Created :
Wed Jul 27 22:48:07
2016
-- Created :
Thu Jul 28 16:59:59
2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_transmission_wb.wb
...
...
@@ -210,6 +210,18 @@ begin
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1101"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
dbg_rx_bvalue_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1110"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
dbg_tx_bvalue_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1111"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
dummy_dummy_i
;
...
...
@@ -273,6 +285,8 @@ begin
-- Debug Start byte
regs_o
.
dbg_ctrl_start_byte_o
<=
wr_transmission_dbg_ctrl_start_byte_int
;
-- Debug content
-- Debug content
-- Debug content
-- DUMMY value to read
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
...
...
wr_transmission_wb.wb
View file @
5fd68a1c
...
...
@@ -242,6 +242,28 @@ peripheral {
access_dev = WRITE_ONLY;
};
};
reg {
name = "DBG RX_BVALUE";
prefix = "DBG_RX_BVALUE";
field {
name = "Debug content";
size = 32;
type =SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "DBG tx bvalue";
prefix = "DBG_TX_BVALUE";
field {
name = "Debug content";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Test value";
prefix = "DUMMY";
...
...
wr_transmission_wbgen2_pkg.vhd
View file @
5fd68a1c
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wr_transmission_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_transmission_wb.wb
-- Created :
Wed Jul 27 22:48:07
2016
-- Created :
Thu Jul 28 16:59:59
2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_transmission_wb.wb
...
...
@@ -33,6 +33,8 @@ package wr_transmission_wbgen2_pkg is
rx_stat7_rx_latency_acc_cnt_i
:
std_logic_vector
(
31
downto
0
);
rx_stat8_rx_lost_block_cnt_i
:
std_logic_vector
(
31
downto
0
);
dbg_data_i
:
std_logic_vector
(
31
downto
0
);
dbg_rx_bvalue_i
:
std_logic_vector
(
31
downto
0
);
dbg_tx_bvalue_i
:
std_logic_vector
(
31
downto
0
);
dummy_dummy_i
:
std_logic_vector
(
31
downto
0
);
end
record
;
...
...
@@ -50,6 +52,8 @@ package wr_transmission_wbgen2_pkg is
rx_stat7_rx_latency_acc_cnt_i
=>
(
others
=>
'0'
),
rx_stat8_rx_lost_block_cnt_i
=>
(
others
=>
'0'
),
dbg_data_i
=>
(
others
=>
'0'
),
dbg_rx_bvalue_i
=>
(
others
=>
'0'
),
dbg_tx_bvalue_i
=>
(
others
=>
'0'
),
dummy_dummy_i
=>
(
others
=>
'0'
)
);
...
...
@@ -112,6 +116,8 @@ tmp.rx_stat6_rx_latency_acc_msb_i := f_x_to_zero(left.rx_stat6_rx_latency_acc_ms
tmp
.
rx_stat7_rx_latency_acc_cnt_i
:
=
f_x_to_zero
(
left
.
rx_stat7_rx_latency_acc_cnt_i
)
or
f_x_to_zero
(
right
.
rx_stat7_rx_latency_acc_cnt_i
);
tmp
.
rx_stat8_rx_lost_block_cnt_i
:
=
f_x_to_zero
(
left
.
rx_stat8_rx_lost_block_cnt_i
)
or
f_x_to_zero
(
right
.
rx_stat8_rx_lost_block_cnt_i
);
tmp
.
dbg_data_i
:
=
f_x_to_zero
(
left
.
dbg_data_i
)
or
f_x_to_zero
(
right
.
dbg_data_i
);
tmp
.
dbg_rx_bvalue_i
:
=
f_x_to_zero
(
left
.
dbg_rx_bvalue_i
)
or
f_x_to_zero
(
right
.
dbg_rx_bvalue_i
);
tmp
.
dbg_tx_bvalue_i
:
=
f_x_to_zero
(
left
.
dbg_tx_bvalue_i
)
or
f_x_to_zero
(
right
.
dbg_tx_bvalue_i
);
tmp
.
dummy_dummy_i
:
=
f_x_to_zero
(
left
.
dummy_dummy_i
)
or
f_x_to_zero
(
right
.
dummy_dummy_i
);
return
tmp
;
end
function
;
...
...
xwr_transmission.vhd
View file @
5fd68a1c
...
...
@@ -344,11 +344,7 @@ begin
end
if
;
end
if
;
end
process
;
-- statistics ideas:
-- * note the timestamp of reset (tai) or number of set frames since reset
-- to make good statistics
regs_to_wb
.
dbg_data_i
<=
dbg_word
;
regs_to_wb
.
dummy_dummy_i
<=
x"DEADBEEF"
;
p_bfield_for_SNMP
:
process
(
clk_sys_i
)
begin
...
...
@@ -371,5 +367,10 @@ begin
snmp_array_o
(
c_STREAMERS_ARR_SIZE_OUT
+
1
)
<=
f_bigEndianess
(
dbg_rx_bfield
);
snmp_array_o
(
c_STREAMERS_ARR_SIZE_OUT
+
2
)
<=
f_bigEndianess
(
dbg_tx_bfield
);
regs_to_wb
.
dbg_data_i
<=
dbg_word
;
regs_to_wb
.
dbg_rx_bvalue_i
<=
f_bigEndianess
(
dbg_rx_bfield
);
regs_to_wb
.
dbg_tx_bvalue_i
<=
f_bigEndianess
(
dbg_tx_bfield
);
regs_to_wb
.
dummy_dummy_i
<=
x"DEADBEEF"
;
end
rtl
;
\ No newline at end of file
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