[wr-cores/wr_streamers] added snapshot option to streamer stats.

t was hard to get fully coherent statistics, especially if they were changing fast (e.g. 250kHz in btrain). Setting snapshot bit to high copies at the same instant all the counters to separate registers. as long as snapshot bit is high, these registers are exposed to WB and SNMP. so one can read it as long as it takes and the data is still coherent. Conflicts: hdl/rtl/WRtransmission/wr_transmission_wb.vhd hdl/rtl/WRtransmission/wr_transmission_wbgen2_pkg.vhd

[wr-cores/wr_streamers] added snapshot option to streamer stats.
t was hard to get fully coherent statistics, especially if they were changing fast (e.g. 250kHz in btrain). Setting snapshot bit to high copies at the same instant all the counters to separate registers. as long as snapshot bit is high, these registers are exposed to WB and SNMP. so one can read it as long as it takes and the data is still coherent. Conflicts: hdl/rtl/WRtransmission/wr_transmission_wb.vhd hdl/rtl/WRtransmission/wr_transmission_wbgen2_pkg.vhd
7ab89921 · Maciej Lipinski · 4f120f31 · 7ab89921 · 7ab89921 · 7ab89921
Commit 7ab89921 authored Jul 27, 2016 by Maciej Lipinski
4 changed files
--- a/wr_transmission_wb.vhd
+++ b/wr_transmission_wb.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : wr_transmission_wb.vhd
 -- Author         : auto-generated by wbgen2 from wr_transmission_wb.wb
-- Created        : Mon Jun 27 11:19:37 2016
+-- Created        : Wed Jul 27 22:48:07 2016
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_transmission_wb.wb
@@ -41,6 +41,7 @@ signal wr_transmission_sscr1_rst_stats_dly0     : std_logic      ;
 signal wr_transmission_sscr1_rst_stats_int      : std_logic      ;
 signal wr_transmission_sscr1_rst_seq_id_dly0    : std_logic      ;
 signal wr_transmission_sscr1_rst_seq_id_int     : std_logic      ;
+signal wr_transmission_sscr1_snapshot_stats_int : std_logic      ;
 signal wr_transmission_dbg_ctrl_mux_int         : std_logic      ;
 signal wr_transmission_dbg_ctrl_start_byte_int  : std_logic_vector(7 downto 0);
 signal ack_sreg                                 : std_logic_vector(9 downto 0);
@@ -72,6 +73,7 @@ begin
      rddata_reg <= "00000000000000000000000000000000";
      wr_transmission_sscr1_rst_stats_int <= '0';
      wr_transmission_sscr1_rst_seq_id_int <= '0';
+      wr_transmission_sscr1_snapshot_stats_int <= '0';
      wr_transmission_dbg_ctrl_mux_int <= '0';
      wr_transmission_dbg_ctrl_start_byte_int <= "00000000";
    elsif rising_edge(clk_sys_i) then
@@ -92,12 +94,13 @@ begin
            if (wb_we_i = '1') then
              wr_transmission_sscr1_rst_stats_int <= wrdata_reg(0);
              wr_transmission_sscr1_rst_seq_id_int <= wrdata_reg(1);
+              wr_transmission_sscr1_snapshot_stats_int <= wrdata_reg(2);
            end if;
            rddata_reg(0) <= '0';
            rddata_reg(1) <= '0';
-            rddata_reg(2) <= regs_i.sscr1_rx_latency_acc_overflow_i;
+            rddata_reg(2) <= wr_transmission_sscr1_snapshot_stats_int;
+            rddata_reg(3) <= regs_i.sscr1_rx_latency_acc_overflow_i;
            rddata_reg(31 downto 4) <= regs_i.sscr1_rst_ts_cyc_i;
-            rddata_reg(3) <= 'X';
            ack_sreg(2) <= '1';
            ack_in_progress <= '1';
          when "0001" => 
@@ -251,6 +254,8 @@ begin
  end process;
  
  
+-- Snapshot statistics
+  regs_o.sscr1_snapshot_stats_o <= wr_transmission_sscr1_snapshot_stats_int;
 -- Latency accumulator overflow
 -- Reset timestamp cycles
 -- Reset timestamp 32 LSB of TAI

--- a/wr_transmission_wb.wb
+++ b/wr_transmission_wb.wb
@@ -46,6 +46,17 @@ peripheral {
      description = "Writing 1 reset sequence ID of transmitted frames";
      type = MONOSTABLE;
    };
+    field {
+      name = "Snapshot statistics";
+      prefix = "SNAPSHOT_STATS";
+      description = "Writing 1 snapshots statistics for reading, it means that all the counters \
+                    are copied at the same instant to registers and this registers can be read\
+                    via wishbone/snmp while the counters are still running in the background. \
+                    this allows to read coherent data";
+      type = BIT;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY; 
+    };
    field {
      name = "Latency accumulator overflow";
      prefix = "RX_LATENCY_ACC_OVERFLOW";

--- a/wr_transmission_wbgen2_pkg.vhd
+++ b/wr_transmission_wbgen2_pkg.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : wr_transmission_wbgen2_pkg.vhd
 -- Author         : auto-generated by wbgen2 from wr_transmission_wb.wb
-- Created        : Mon Jun 27 11:19:37 2016
+-- Created        : Wed Jul 27 22:48:07 2016
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_transmission_wb.wb
@@ -58,6 +58,7 @@ package wr_transmission_wbgen2_pkg is
    type t_wr_transmission_out_registers is record
      sscr1_rst_stats_o                        : std_logic;
      sscr1_rst_seq_id_o                       : std_logic;
+      sscr1_snapshot_stats_o                   : std_logic;
      dbg_ctrl_mux_o                           : std_logic;
      dbg_ctrl_start_byte_o                    : std_logic_vector(7 downto 0);
      end record;
@@ -65,6 +66,7 @@ package wr_transmission_wbgen2_pkg is
    constant c_wr_transmission_out_registers_init_value: t_wr_transmission_out_registers := (
      sscr1_rst_stats_o => '0',
      sscr1_rst_seq_id_o => '0',
+      sscr1_snapshot_stats_o => '0',
      dbg_ctrl_mux_o => '0',
      dbg_ctrl_start_byte_o => (others => '0')
      );

--- a/xwr_transmission.vhd
+++ b/xwr_transmission.vhd
@@ -270,6 +270,7 @@ begin
      tm_tai_i                 => tm_tai_i,
      tm_cycles_i              => tm_cycles_i,
      reset_stats_i            => regs_from_wb.sscr1_rst_stats_o,
+      snapshot_ena_i           => regs_from_wb.sscr1_snapshot_stats_o,
      reset_time_tai_o         => reset_time_tai,
      reset_time_cycles_o      => regs_to_wb.sscr1_rst_ts_cyc_i,
      sent_frame_cnt_o         => regs_to_wb.tx_stat_tx_sent_cnt_i,
@@ -366,7 +367,7 @@ begin
    end if;
  end process;  

-  snmp_array_o(c_STREAMERS_ARR_SIZE_OUT)   <= dbg_word
+  snmp_array_o(c_STREAMERS_ARR_SIZE_OUT)   <= dbg_word;
  snmp_array_o(c_STREAMERS_ARR_SIZE_OUT+1) <= f_bigEndianess(dbg_rx_bfield);
  snmp_array_o(c_STREAMERS_ARR_SIZE_OUT+2) <= f_bigEndianess(dbg_tx_bfield);