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White Rabbit core collection
Commit 5ba6b9d5 authored by Maciej Lipinski's avatar Maciej Lipinski
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[board/all] assign default zero to clk_ext_i, needed when not used

parent 6f4529b4
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Showing with 9 additions and 9 deletions
board/spec/wr_spec_pkg.vhd
View file @ 5ba6b9d5
......@@ -74,7 +74,7 @@ package wr_spec_pkg is
wrs_rx_dreq_i : in std_logic := '0';
wb_eth_master_o : out t_wishbone_master_out;
wb_eth_master_i : in t_wishbone_master_in := cc_dummy_master_in;
pps_ext_i : in std_logic;
pps_ext_i : in std_logic := '0';
pps_p_o : out std_logic;
pps_led_o : out std_logic;
tm_time_valid_o : out std_logic;
......
board/spec/wrc_board_spec.vhd
View file @ 5ba6b9d5
......@@ -235,7 +235,7 @@ entity wrc_board_spec is
-- WRPC timing interface and status
---------------------------------------------------------------------------
pps_ext_i : in std_logic;
pps_ext_i : in std_logic := '0';
pps_p_o : out std_logic;
pps_led_o : out std_logic;
tm_time_valid_o : out std_logic;
......
board/spec/xwrc_board_spec.vhd
View file @ 5ba6b9d5
......@@ -200,7 +200,7 @@ entity xwrc_board_spec is
-- WRPC timing interface and status
---------------------------------------------------------------------------
pps_ext_i : in std_logic;
pps_ext_i : in std_logic := '0';
pps_p_o : out std_logic;
pps_led_o : out std_logic;
tm_time_valid_o : out std_logic;
......
board/svec/wr_svec_pkg.vhd
View file @ 5ba6b9d5
......@@ -75,7 +75,7 @@ package wr_svec_pkg is
wrs_rx_dreq_i : in std_logic := '0';
wb_eth_master_o : out t_wishbone_master_out;
wb_eth_master_i : in t_wishbone_master_in := cc_dummy_master_in;
pps_ext_i : in std_logic;
pps_ext_i : in std_logic := '0';
pps_p_o : out std_logic;
pps_led_o : out std_logic;
tm_time_valid_o : out std_logic;
......
board/svec/wrc_board_svec.vhd
View file @ 5ba6b9d5
......@@ -237,7 +237,7 @@ entity wrc_board_svec is
-- WRPC timing interface and status
---------------------------------------------------------------------------
pps_ext_i : in std_logic;
pps_ext_i : in := '0';
pps_p_o : out std_logic;
pps_led_o : out std_logic;
tm_time_valid_o : out std_logic;
......
board/svec/xwrc_board_svec.vhd
View file @ 5ba6b9d5
......@@ -202,7 +202,7 @@ entity xwrc_board_svec is
-- WRPC timing interface and status
---------------------------------------------------------------------------
pps_ext_i : in std_logic;
pps_ext_i : in std_logic := '0';
pps_p_o : out std_logic;
pps_led_o : out std_logic;
tm_time_valid_o : out std_logic;
......
board/vfchd/wr_vfchd_pkg.vhd
View file @ 5ba6b9d5
......@@ -156,7 +156,7 @@ package wr_vfchd_pkg is
wb_eth_err_i : in std_logic := '0';
wb_eth_rty_i : in std_logic := '0';
wb_eth_stall_i : in std_logic := '0';
pps_ext_i : in std_logic;
pps_ext_i : in std_logic := '0';
pps_p_o : out std_logic;
pps_led_o : out std_logic;
tm_time_valid_o : out std_logic;
......
board/vfchd/wrc_board_vfchd.vhd
View file @ 5ba6b9d5
......@@ -216,7 +216,7 @@ entity wrc_board_vfchd is
-- WRPC timing interface and status
---------------------------------------------------------------------------
pps_ext_i : in std_logic;
pps_ext_i : in std_logic := '0';
pps_p_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
......
board/vfchd/xwrc_board_vfchd.vhd
View file @ 5ba6b9d5
......@@ -178,7 +178,7 @@ entity xwrc_board_vfchd is
-- WRPC timing interface and status
---------------------------------------------------------------------------
pps_ext_i : in std_logic;
pps_ext_i : in std_logic := '0';
pps_p_o : out std_logic;
pps_led_o : out std_logic;
tm_time_valid_o : out std_logic;
......
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