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White Rabbit core collection
Commit 4fd10123 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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wrc_syscon: updated wb slave interface with latest wbgen

parent ebf189f5
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modules/wrc_core/wrc_syscon_pkg.vhd
View file @ 4fd10123
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_syscon_pkg.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created : Fri Feb 17 19:23:19 2012
-- Created : Thu Aug 2 11:41:11 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -96,6 +96,7 @@ package sysc_wbgen2_pkg is
);
function "or" (left, right: t_sysc_in_registers) return t_sysc_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body sysc_wbgen2_pkg is
......@@ -107,19 +108,31 @@ else
return x;
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_sysc_in_registers) return t_sysc_in_registers is
variable tmp: t_sysc_in_registers;
begin
tmp.gpsr_fmc_scl_i := left.gpsr_fmc_scl_i or right.gpsr_fmc_scl_i;
tmp.gpsr_fmc_sda_i := left.gpsr_fmc_sda_i or right.gpsr_fmc_sda_i;
tmp.gpsr_btn1_i := left.gpsr_btn1_i or right.gpsr_btn1_i;
tmp.gpsr_btn2_i := left.gpsr_btn2_i or right.gpsr_btn2_i;
tmp.gpsr_sfp_det_i := left.gpsr_sfp_det_i or right.gpsr_sfp_det_i;
tmp.gpsr_sfp_scl_i := left.gpsr_sfp_scl_i or right.gpsr_sfp_scl_i;
tmp.gpsr_sfp_sda_i := left.gpsr_sfp_sda_i or right.gpsr_sfp_sda_i;
tmp.hwfr_memsize_i := left.hwfr_memsize_i or right.hwfr_memsize_i;
tmp.tcr_tdiv_i := left.tcr_tdiv_i or right.tcr_tdiv_i;
tmp.tvr_i := left.tvr_i or right.tvr_i;
tmp.gpsr_fmc_scl_i := f_x_to_zero(left.gpsr_fmc_scl_i) or f_x_to_zero(right.gpsr_fmc_scl_i);
tmp.gpsr_fmc_sda_i := f_x_to_zero(left.gpsr_fmc_sda_i) or f_x_to_zero(right.gpsr_fmc_sda_i);
tmp.gpsr_btn1_i := f_x_to_zero(left.gpsr_btn1_i) or f_x_to_zero(right.gpsr_btn1_i);
tmp.gpsr_btn2_i := f_x_to_zero(left.gpsr_btn2_i) or f_x_to_zero(right.gpsr_btn2_i);
tmp.gpsr_sfp_det_i := f_x_to_zero(left.gpsr_sfp_det_i) or f_x_to_zero(right.gpsr_sfp_det_i);
tmp.gpsr_sfp_scl_i := f_x_to_zero(left.gpsr_sfp_scl_i) or f_x_to_zero(right.gpsr_sfp_scl_i);
tmp.gpsr_sfp_sda_i := f_x_to_zero(left.gpsr_sfp_sda_i) or f_x_to_zero(right.gpsr_sfp_sda_i);
tmp.hwfr_memsize_i := f_x_to_zero(left.hwfr_memsize_i) or f_x_to_zero(right.hwfr_memsize_i);
tmp.tcr_tdiv_i := f_x_to_zero(left.tcr_tdiv_i) or f_x_to_zero(right.tcr_tdiv_i);
tmp.tvr_i := f_x_to_zero(left.tvr_i) or f_x_to_zero(right.tvr_i);
return tmp;
end function;
end package body;
modules/wrc_core/wrc_syscon_wb.vhd
View file @ 4fd10123
This diff is collapsed.
modules/wrc_core/xwr_syscon_wb.vhd
View file @ 4fd10123
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-11-07
-- Last update: 2012-07-09
-- Last update: 2012-08-02
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -49,15 +49,16 @@ architecture syn of xwr_syscon_wb is
component wrc_syscon_wb
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(2 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_sysc_in_registers;
regs_o : out t_sysc_out_registers
);
......@@ -94,15 +95,16 @@ begin
WRAPPED_SYSCON: wrc_syscon_wb
port map(
rst_n_i => rst_n_i,
wb_clk_i => clk_sys_i,
wb_addr_i => wb_in.adr(2 downto 0),
wb_data_i => wb_in.dat,
wb_data_o => wb_out.dat,
clk_sys_i => clk_sys_i,
wb_adr_i => wb_in.adr(2 downto 0),
wb_dat_i => wb_in.dat,
wb_dat_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
wb_stall_o => wb_out.stall,
regs_i => regs_i,
regs_o => regs_o);
......
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