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White Rabbit core collection
Commit ebf189f5 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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wr_mini_nic: updated wb slave interface with latest wbgen

parent 2fc4de68
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Showing with 273 additions and 278 deletions
modules/wr_mini_nic/minic_wb_slave.vhd
View file @ ebf189f5
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modules/wr_mini_nic/minic_wbgen2_pkg.vhd
View file @ ebf189f5
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : minic_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from mini_nic.wb
-- Created : Tue May 29 15:57:15 2012
-- Created : Thu Aug 2 12:16:40 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
......@@ -89,6 +89,7 @@ package minic_wbgen2_pkg is
);
function "or" (left, right: t_minic_in_registers) return t_minic_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body minic_wbgen2_pkg is
......@@ -100,23 +101,35 @@ else
return x;
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_minic_in_registers) return t_minic_in_registers is
variable tmp: t_minic_in_registers;
begin
tmp.mcr_tx_idle_i := left.mcr_tx_idle_i or right.mcr_tx_idle_i;
tmp.mcr_tx_error_i := left.mcr_tx_error_i or right.mcr_tx_error_i;
tmp.mcr_rx_ready_i := left.mcr_rx_ready_i or right.mcr_rx_ready_i;
tmp.mcr_rx_full_i := left.mcr_rx_full_i or right.mcr_rx_full_i;
tmp.tx_addr_i := left.tx_addr_i or right.tx_addr_i;
tmp.rx_addr_i := left.rx_addr_i or right.rx_addr_i;
tmp.rx_size_i := left.rx_size_i or right.rx_size_i;
tmp.rx_avail_i := left.rx_avail_i or right.rx_avail_i;
tmp.tsr0_valid_i := left.tsr0_valid_i or right.tsr0_valid_i;
tmp.tsr0_pid_i := left.tsr0_pid_i or right.tsr0_pid_i;
tmp.tsr0_fid_i := left.tsr0_fid_i or right.tsr0_fid_i;
tmp.tsr1_tsval_i := left.tsr1_tsval_i or right.tsr1_tsval_i;
tmp.dbgr_irq_cnt_i := left.dbgr_irq_cnt_i or right.dbgr_irq_cnt_i;
tmp.dbgr_wb_irq_val_i := left.dbgr_wb_irq_val_i or right.dbgr_wb_irq_val_i;
tmp.mcr_tx_idle_i := f_x_to_zero(left.mcr_tx_idle_i) or f_x_to_zero(right.mcr_tx_idle_i);
tmp.mcr_tx_error_i := f_x_to_zero(left.mcr_tx_error_i) or f_x_to_zero(right.mcr_tx_error_i);
tmp.mcr_rx_ready_i := f_x_to_zero(left.mcr_rx_ready_i) or f_x_to_zero(right.mcr_rx_ready_i);
tmp.mcr_rx_full_i := f_x_to_zero(left.mcr_rx_full_i) or f_x_to_zero(right.mcr_rx_full_i);
tmp.tx_addr_i := f_x_to_zero(left.tx_addr_i) or f_x_to_zero(right.tx_addr_i);
tmp.rx_addr_i := f_x_to_zero(left.rx_addr_i) or f_x_to_zero(right.rx_addr_i);
tmp.rx_size_i := f_x_to_zero(left.rx_size_i) or f_x_to_zero(right.rx_size_i);
tmp.rx_avail_i := f_x_to_zero(left.rx_avail_i) or f_x_to_zero(right.rx_avail_i);
tmp.tsr0_valid_i := f_x_to_zero(left.tsr0_valid_i) or f_x_to_zero(right.tsr0_valid_i);
tmp.tsr0_pid_i := f_x_to_zero(left.tsr0_pid_i) or f_x_to_zero(right.tsr0_pid_i);
tmp.tsr0_fid_i := f_x_to_zero(left.tsr0_fid_i) or f_x_to_zero(right.tsr0_fid_i);
tmp.tsr1_tsval_i := f_x_to_zero(left.tsr1_tsval_i) or f_x_to_zero(right.tsr1_tsval_i);
tmp.dbgr_irq_cnt_i := f_x_to_zero(left.dbgr_irq_cnt_i) or f_x_to_zero(right.dbgr_irq_cnt_i);
tmp.dbgr_wb_irq_val_i := f_x_to_zero(left.dbgr_wb_irq_val_i) or f_x_to_zero(right.dbgr_wb_irq_val_i);
return tmp;
end function;
end package body;
modules/wr_mini_nic/wr_mini_nic.vhd
View file @ ebf189f5
......@@ -107,7 +107,7 @@ entity wr_mini_nic is
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_irq_o : out std_logic
wb_int_o : out std_logic
);
end wr_mini_nic;
......@@ -116,16 +116,17 @@ architecture behavioral of wr_mini_nic is
component minic_wb_slave
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(4 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_irq_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
tx_ts_read_ack_o : out std_logic;
irq_tx_i : in std_logic;
irq_tx_ack_o : out std_logic;
......@@ -134,7 +135,8 @@ architecture behavioral of wr_mini_nic is
irq_rx_ack_o : out std_logic;
irq_txts_i : in std_logic;
regs_i : in t_minic_in_registers;
regs_o : out t_minic_out_registers);
regs_o : out t_minic_out_registers
);
end component;
--type t_wrf_status_reg is record
......@@ -1153,16 +1155,17 @@ begin -- behavioral
U_WB_Slave : minic_wb_slave
port map (
rst_n_i => rst_n_i,
wb_clk_i => clk_sys_i,
wb_addr_i => wb_out.adr(4 downto 0),
wb_data_i => wb_out.dat,
wb_data_o => wb_in.dat,
clk_sys_i => clk_sys_i,
wb_adr_i => wb_out.adr(4 downto 0),
wb_dat_i => wb_out.dat,
wb_dat_o => wb_in.dat,
wb_cyc_i => wb_out.cyc,
wb_sel_i => wb_out.sel,
wb_stb_i => wb_out.stb,
wb_we_i => wb_out.we,
wb_ack_o => wb_in.ack,
wb_irq_o => wb_irq_o,
wb_stall_o => wb_in.stall,
wb_int_o => wb_int_o,
regs_i => regs_in,
regs_o => regs_out,
tx_ts_read_ack_o => open,
......
modules/wr_mini_nic/xwr_mini_nic.vhd
View file @ ebf189f5
......@@ -105,7 +105,7 @@ architecture wrapper of xwr_mini_nic is
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_irq_o : out std_logic);
wb_int_o : out std_logic);
end component;
begin -- wrapper
......@@ -156,7 +156,7 @@ begin -- wrapper
wb_dat_o => wb_o.dat,
wb_ack_o => wb_o.ack,
wb_stall_o => wb_o.stall,
wb_irq_o => wb_o.int);
wb_int_o => wb_o.int);
wb_o.err <= '0';
......
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