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White Rabbit core collection
Commit 486125a0 authored by A. Hahn's avatar A. Hahn
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merge: get current state from wrpc-v5 branch

parent 7dbca830
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    modules/wr_eca/eca_wb_event.vhd
    View file @ 486125a0
    ......@@ -2,7 +2,7 @@
    --! @brief ECA Event stream
    --! @author Wesley W. Terpstra <w.terpstra@gsi.de>
    --!
    --! Copyright (C) 2013 GSI Helmholtz Centre for Heavy Ion Research GmbH
    --! Copyright (C) 2013 GSI Helmholtz Centre for Heavy Ion Research GmbH
    --!
    --! Feed chunks of 8 words in from the Wishbone clock domain.
    --! If the queue cannot fit 8 words, spit out errors until cycle end.
    ......@@ -18,7 +18,7 @@
    --! but WITHOUT ANY WARRANTY; without even the implied warranty of
    --! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
    --! Lesser General Public License for more details.
    --!
    --!
    --! You should have received a copy of the GNU Lesser General Public
    --! License along with this library. If not, see <http://www.gnu.org/licenses/>.
    ---------------------------------------------------------------------------------
    ......@@ -44,9 +44,9 @@ end eca_wb_event;
    architecture rtl of eca_wb_event is
    -- Out of principle, tell quartus to leave my design alone.
    attribute altera_attribute : string;
    attribute altera_attribute : string;
    attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
    -- We track two kinds of pointers:
    -- Event pointers count completed writes of 8 words
    -- Word pointers are indexes into the FIFO
    ......@@ -56,33 +56,33 @@ architecture rtl of eca_wb_event is
    -- where re_ready is an old value of rw_ready; behind only by clock-crossing delay
    -- and rw_limit is an old value of rw_sent+7; behind by 1 clock cycle
    -- and rw_sent is an old value of re_sent; behind only by clock-crossing delay
    constant c_addr1_bits : natural := 5;
    constant c_addr5_bits : natural := c_addr1_bits - 2;
    subtype t_addr1 is unsigned(c_addr1_bits-1 downto 0);
    subtype t_addr5 is unsigned(c_addr5_bits-1 downto 0);
    type t_state is (S0, S1, S2, S3, S4, S5, S6, S7, SERR);
    -- Registers in clock domain w_clk_i
    signal rw_ready_gray : t_addr5;
    signal rw1_sent_gray : t_addr5;
    signal rw0_sent_gray : t_addr5;
    signal rw_sent : t_addr5;
    signal rw_limit : t_addr5;
    signal rw_ready : t_addr5 := (others => '0');
    signal rw_state : t_state := S0;
    signal rw_addr : t_addr1 := (others => '0');
    signal rw_ok : t_addr1 := (others => '0');
    -- Registers in clock domain e_clk_i
    signal re_sent_gray : t_addr5;
    signal re1_ready_gray : t_addr5;
    signal re0_ready_gray : t_addr5;
    signal re_ready : t_addr5;
    signal re_sent : t_addr5 := (others => '0');
    signal re_state : t_state := S0;
    signal re_stb : std_logic := '0';
    ......@@ -91,7 +91,7 @@ architecture rtl of eca_wb_event is
    signal re_param : t_param := (others => '0');
    signal re_tef : t_tef := (others => '0');
    signal re_time : t_time := (others => '0');
    -- Signals in clock domain e_clk_i
    signal se_exit_s0 : boolean;
    signal se_addr : t_addr1;
    ......@@ -123,24 +123,24 @@ begin
    begin
    if rising_edge(w_clk_i) then
    rw_ready_gray <= unsigned(f_eca_gray_encode(std_logic_vector(rw_ready)));-- To domain E
    rw1_sent_gray <= re_sent_gray; -- From domain E
    rw0_sent_gray <= rw1_sent_gray;
    rw_sent <= unsigned(f_eca_gray_decode(std_logic_vector(rw0_sent_gray), 1));
    rw_limit <= rw_sent + 7;
    vw_addr1 := rw_addr + 1;
    w_slave_o.ACK <= '0';
    w_slave_o.ERR <= '0';
    if w_rst_n_i = '0' then
    rw_ready <= (others => '0');
    rw_state <= S0;
    rw_addr <= (others => '0');
    rw_ok <= (others => '0');
    else
    if w_slave_i.CYC = '0' then
    rw_state <= S0;
    rw_addr <= rw_ok;
    ......@@ -150,7 +150,7 @@ begin
    w_slave_o.ACK <= '1'; -- Reading always works
    else
    case rw_state is
    when S0 =>
    when S0 =>
    -- If w_clk_i is fast, then fanout from comparison might cost...
    if rw_ready = rw_limit then
    rw_state <= SERR;
    ......@@ -160,45 +160,45 @@ begin
    w_slave_o.ACK <= '1';
    rw_addr <= vw_addr1;
    end if;
    when S1 =>
    rw_state <= S2;
    w_slave_o.ACK <= '1';
    rw_addr <= vw_addr1;
    when S2 =>
    rw_state <= S3;
    w_slave_o.ACK <= '1';
    rw_addr <= vw_addr1;
    when S3 =>
    rw_state <= S4;
    w_slave_o.ACK <= '1';
    rw_addr <= vw_addr1;
    when S4 =>
    rw_state <= S5;
    w_slave_o.ACK <= '1';
    rw_addr <= vw_addr1;
    when S5 =>
    rw_state <= S6;
    w_slave_o.ACK <= '1';
    rw_addr <= vw_addr1;
    when S6 =>
    rw_state <= S7;
    w_slave_o.ACK <= '1';
    rw_addr <= vw_addr1;
    when S7 =>
    rw_state <= S0;
    w_slave_o.ACK <= '1';
    rw_addr <= vw_addr1;
    rw_ready <= rw_ready + 1;
    rw_ok <= vw_addr1;
    when SERR =>
    w_slave_o.ERR <= '1';
    end case;
    ......@@ -208,90 +208,90 @@ begin
    end if; -- reset
    end if; -- clock
    end process;
    e_stream_o.stb <= re_stb;
    e_stream_o.event <= re_event;
    e_stream_o.param <= re_param;
    e_stream_o.tef <= re_tef;
    e_stream_o.time <= re_time;
    -- This cannot be inside the process because both re_addr and Q.r_addr_i latch se_addr
    se_exit_s0 <= (re_sent /= re_ready) and (re_stb = '0' or e_stall_i = '0');
    se_addr <=
    se_addr <=
    re_addr when (re_state=S0 and not se_exit_s0) else
    (re_addr + 1);
    E : process(e_clk_i) is
    begin
    if rising_edge(e_clk_i) then
    re_sent_gray <= unsigned(f_eca_gray_encode(std_logic_vector(re_sent))); -- to domain W
    re1_ready_gray <= rw_ready_gray; -- from domain W
    re0_ready_gray <= re1_ready_gray;
    re_ready <= unsigned(f_eca_gray_decode(std_logic_vector(re0_ready_gray), 1));
    if e_rst_n_i = '0' then
    re_event <= (others => '0');
    re_param <= (others => '0');
    re_tef <= (others => '0');
    re_time <= (others => '0');
    re_sent <= (others => '0');
    re_state <= S0;
    re_stb <= '0';
    re_addr <= (others => '0');
    else
    re_addr <= se_addr;
    case re_state is
    when S0 =>
    when S0 =>
    if re_stb = '1' and e_stall_i = '0' then
    re_stb <= '0';
    end if;
    if re_stb = '0' or e_stall_i = '0' then
    re_event(63 downto 32) <= se_data;
    end if;
    if se_exit_s0 then
    re_state <= S1;
    end if;
    when S1 =>
    re_event(31 downto 0) <= se_data;
    re_state <= S2;
    when S2 =>
    re_param(63 downto 32) <= se_data;
    re_state <= S3;
    when S3 =>
    re_param(31 downto 0) <= se_data;
    re_state <= S4;
    when S4 =>
    -- reserved bits against future changes
    re_state <= S5;
    when S5 =>
    re_tef(31 downto 0) <= se_data;
    re_state <= S6;
    when S6 =>
    re_time(63 downto 32) <= se_data;
    re_state <= S7;
    when S7 =>
    re_time(31 downto 0) <= se_data;
    re_state <= S0;
    re_stb <= '1';
    re_sent <= re_sent + 1;
    when SERR => null; -- unreachable
    end case;
    end if;
    end if;
    end process;
    end rtl;
    modules/wr_endpoint/wr_endpoint.vhd
    View file @ 486125a0
    ......@@ -15,27 +15,27 @@
    -- features such as:
    -- - VLANs: inserting/removing tags (for ACCESS/TRUNK port support)
    -- - RX/TX precise timestaping
    -- - full PCS for optical Gigabit Ethernet
    -- - full PCS for optical Gigabit Ethernet
    -- - decodes MAC addresses, VIDs and priorities and passes them to the RTU.
    -- Refer to the manual for more details.
    -------------------------------------------------------------------------------
    --
    -- Copyright (c) 2011 - 2017 CERN / BE-CO-HT
    --
    -- This source file is free software; you can redistribute it
    -- and/or modify it under the terms of the GNU Lesser General
    -- Public License as published by the Free Software Foundation;
    -- either version 2.1 of the License, or (at your option) any
    -- later version.
    -- This source file is free software; you can redistribute it
    -- and/or modify it under the terms of the GNU Lesser General
    -- Public License as published by the Free Software Foundation;
    -- either version 2.1 of the License, or (at your option) any
    -- later version.
    --
    -- This source is distributed in the hope that it will be
    -- useful, but WITHOUT ANY WARRANTY; without even the implied
    -- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
    -- PURPOSE. See the GNU Lesser General Public License for more
    -- details.
    -- This source is distributed in the hope that it will be
    -- useful, but WITHOUT ANY WARRANTY; without even the implied
    -- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
    -- PURPOSE. See the GNU Lesser General Public License for more
    -- details.
    --
    -- You should have received a copy of the GNU Lesser General
    -- Public License along with this source; if not, download it
    -- You should have received a copy of the GNU Lesser General
    -- Public License along with this source; if not, download it
    -- from http://www.gnu.org/licenses/lgpl-2.1.html
    --
    -------------------------------------------------------------------------------
    ......@@ -54,7 +54,7 @@ use work.wr_fabric_pkg.all;
    use work.wishbone_pkg.all;
    entity wr_endpoint is
    generic (
    g_interface_mode : t_wishbone_interface_mode := CLASSIC;
    g_address_granularity : t_wishbone_address_granularity := WORD;
    ......@@ -109,7 +109,7 @@ entity wr_endpoint is
    -------------------------------------------------------------------------------
    -- PHY Interace (8/16 bit PCS)
    -------------------------------------------------------------------------------
    -------------------------------------------------------------------------------
    phy_rst_o : out std_logic;
    phy_loopen_o : out std_logic;
    ......@@ -175,7 +175,7 @@ entity wr_endpoint is
    -------------------------------------------------------------------------------
    -- TX timestamping unit interface
    -------------------------------------------------------------------------------
    -------------------------------------------------------------------------------
    -- Port ID value
    txtsu_port_id_o : out std_logic_vector(4 downto 0);
    ......@@ -206,9 +206,9 @@ entity wr_endpoint is
    -- 1 indicates that coresponding RTU port is almost full.
    rtu_almost_full_i : in std_logic;
    -- request strobe, single HI pulse begins evaluation of the request.
    -- request strobe, single HI pulse begins evaluation of the request.
    rtu_rq_strobe_p1_o : out std_logic;
    rtu_rq_abort_o : out std_logic;
    -- source and destination MAC addresses extracted from the packet header
    ......@@ -228,7 +228,7 @@ entity wr_endpoint is
    -- HI indicates that packet has assigned priority.
    rtu_rq_has_prio_o : out std_logic;
    -------------------------------------------------------------------------------
    -------------------------------------------------------------------------------
    -- Wishbone bus
    -------------------------------------------------------------------------------
    ......@@ -251,7 +251,7 @@ entity wr_endpoint is
    pfilter_done_o : out std_logic;
    -------------------------------------------------------------------------------
    -- control of PAUSE sending (ML: not used and not tested... TRU uses packet injection) --
    -- control of PAUSE sending (ML: not used and not tested... TRU uses packet injection) --
    -------------------------------------------------------------------------------
    fc_tx_pause_req_i : in std_logic := '0';
    ......@@ -299,7 +299,7 @@ entity wr_endpoint is
    -- HI physically kills the link (turn of laser)
    link_kill_i : in std_logic := '0';
    -- HI indicates that link is up (so cable connected), LOW indicates that link is faulty
    -- HI indicates that link is up (so cable connected), LOW indicates that link is faulty
    -- (e.g.: cable disconnected)
    link_up_o : out std_logic;
    ......@@ -795,7 +795,7 @@ begin
    regs_o => regs_fromwb,
    regs_i => regs_towb
    );
    );
    wb_out.stall <= '0';
    wb_out.rty <= '0';
    ......@@ -839,7 +839,7 @@ begin
    -------------------------------------------------------------------------------
    -- DMTD phase meter
    ------------------------------------------------------------------------------
    ------------------------------------------------------------------------------
    gen_with_dmtd : if(g_with_dmtd) generate
    U_DMTD : dmtd_phase_meas
    ......@@ -1013,7 +1013,7 @@ begin
    -- TRIG1 => TRIG1,
    -- TRIG2 => TRIG2,
    -- TRIG3 => TRIG3);
    --
    --
    -- TRIG0(15 downto 0) <= phy_rx_data_i;
    -- TRIG0(17 downto 16) <= phy_rx_k_i;
    -- TRIG0( 18) <= phy_rx_enc_err_i;
    ......@@ -1025,3 +1025,5 @@ begin
    gmii_tx_er_o <= '0';
    end syn;
    modules/wr_softpll_ng/wr_softpll_ng.vhd
    View file @ 486125a0
    This diff is collapsed.
    modules/wr_softpll_ng/xwr_softpll_ng.vhd
    View file @ 486125a0
    ......@@ -10,27 +10,27 @@
    -- Platform : FPGA-generic
    -- Standard : VHDL'93
    -------------------------------------------------------------------------------
    -- Description:
    -- Description:
    --
    -- Struct'ized version of wr_softpll_ng.
    -------------------------------------------------------------------------------
    --
    -- Copyright (c) 2012-2017 CERN
    --
    -- This source file is free software; you can redistribute it
    -- and/or modify it under the terms of the GNU Lesser General
    -- Public License as published by the Free Software Foundation;
    -- either version 2.1 of the License, or (at your option) any
    -- later version.
    -- This source file is free software; you can redistribute it
    -- and/or modify it under the terms of the GNU Lesser General
    -- Public License as published by the Free Software Foundation;
    -- either version 2.1 of the License, or (at your option) any
    -- later version.
    --
    -- This source is distributed in the hope that it will be
    -- useful, but WITHOUT ANY WARRANTY; without even the implied
    -- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
    -- PURPOSE. See the GNU Lesser General Public License for more
    -- details.
    -- This source is distributed in the hope that it will be
    -- useful, but WITHOUT ANY WARRANTY; without even the implied
    -- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
    -- PURPOSE. See the GNU Lesser General Public License for more
    -- details.
    --
    -- You should have received a copy of the GNU Lesser General
    -- Public License along with this source; if not, download it
    -- You should have received a copy of the GNU Lesser General
    -- Public License along with this source; if not, download it
    -- from http://www.gnu.org/licenses/lgpl-2.1.html
    --
    -------------------------------------------------------------------------------
    ......@@ -56,17 +56,15 @@ entity xwr_softpll_ng is
    -- These two are obvious:
    g_num_ref_inputs : integer := 1;
    g_num_outputs : integer := 1;
    -- Number of external channels (e.g. 2 for WR Switch for regular and low-jitter
    -- ext channel)
    g_num_exts : integer := 1;
    -- When true, an additional FIFO is instantiated, providing a realtime record
    -- of user-selectable SoftPLL parameters (e.g. tag values, phase error, DAC drive).
    -- These values can be read by "spll_dbg_proxy" daemon for further analysis.
    g_with_debug_fifo : boolean := false;
    -- When true, an additional accumulating bang-bang phase detector is instantiated
    -- for wideband locking of the local oscillator to an external stable reference
    -- (e.g. GPSDO/Cesium 10 MHz)
    g_with_ext_clock_input : boolean := false;
    -- When true, DDMTD inputs are reverse (so that the DDMTD offset clocks is
    -- being sampled by the measured clock). This is functionally equivalent to
    -- "direct" operation, but may improve FPGA timing/routability.
    ......@@ -79,6 +77,8 @@ entity xwr_softpll_ng is
    g_ref_clock_rate : integer := 125000000;
    g_ext_clock_rate : integer := 10000000;
    g_use_sampled_ref_clocks : boolean := false;
    g_interface_mode : t_wishbone_interface_mode := PIPELINED;
    g_address_granularity : t_wishbone_address_granularity := BYTE
    );
    ......@@ -92,17 +92,21 @@ entity xwr_softpll_ng is
    -- Reference inputs (i.e. the RX clocks recovered by the PHYs)
    clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
    -- Reference inputs (i.e. the RX clocks recovered by the PHYs), externally sampled
    clk_ref_sampled_i : in std_logic_vector(g_num_ref_inputs-1 downto 0) := (others => '0');
    -- Feedback clocks (i.e. the outputs of the main or aux oscillator)
    clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
    -- DMTD Offset clock
    clk_dmtd_i : in std_logic;
    -- External reference clock (e.g. 10 MHz from Cesium/GPSDO). Used only if
    -- g_with_ext_clock_input == true
    -- g_num_exts > 0
    clk_ext_i : in std_logic;
    -- External clock, multiplied to 125 MHz using the FPGA's PLL
    clk_ext_mul_i : in std_logic;
    clk_ext_mul_i : in std_logic_vector(f_nonzero_vector(g_num_exts)-1 downto 0);
    clk_ext_mul_locked_i : in std_logic := '1';
    clk_ext_stopped_i : in std_logic := '0';
    clk_ext_rst_o : out std_logic;
    ......@@ -144,12 +148,13 @@ architecture wrapper of xwr_softpll_ng is
    g_dac_bits : integer;
    g_num_ref_inputs : integer;
    g_num_outputs : integer;
    g_num_exts : integer;
    g_with_debug_fifo : boolean;
    g_with_ext_clock_input : boolean;
    g_reverse_dmtds : boolean;
    g_divide_input_by_2 : boolean;
    g_ref_clock_rate : integer;
    g_ext_clock_rate : integer;
    g_use_sampled_ref_clocks : boolean;
    g_interface_mode : t_wishbone_interface_mode;
    g_address_granularity : t_wishbone_address_granularity);
    port (
    ......@@ -159,10 +164,11 @@ architecture wrapper of xwr_softpll_ng is
    rst_ext_n_i : in std_logic;
    rst_dmtd_n_i : in std_logic;
    clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
    clk_ref_sampled_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
    clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
    clk_dmtd_i : in std_logic;
    clk_ext_i : in std_logic;
    clk_ext_mul_i : in std_logic;
    clk_ext_mul_i : in std_logic_vector(f_nonzero_vector(g_num_exts)-1 downto 0);
    clk_ext_mul_locked_i : in std_logic;
    clk_ext_stopped_i : in std_logic;
    clk_ext_rst_o : out std_logic;
    ......@@ -185,11 +191,11 @@ architecture wrapper of xwr_softpll_ng is
    wb_we_i : in std_logic;
    wb_ack_o : out std_logic;
    wb_stall_o : out std_logic;
    wb_irq_o : out std_logic;
    irq_o : out std_logic;
    debug_o : out std_logic_vector(5 downto 0);
    dbg_fifo_irq_o : out std_logic);
    end component;
    begin -- behavioral
    U_Wrapped_Softpll : wr_softpll_ng
    ......@@ -200,12 +206,13 @@ begin -- behavioral
    g_address_granularity => g_address_granularity,
    g_num_ref_inputs => g_num_ref_inputs,
    g_num_outputs => g_num_outputs,
    g_num_exts => g_num_exts,
    g_with_debug_fifo => g_with_debug_fifo,
    g_with_ext_clock_input => g_with_ext_clock_input,
    g_reverse_dmtds => g_reverse_dmtds,
    g_divide_input_by_2 => g_divide_input_by_2,
    g_ref_clock_rate => g_ref_clock_rate,
    g_ext_clock_rate => g_ext_clock_rate
    g_use_sampled_ref_clocks => g_use_sampled_ref_clocks,
    g_ref_clock_rate => g_ref_clock_rate,
    g_ext_clock_rate => g_ext_clock_rate
    )
    port map (
    clk_sys_i => clk_sys_i,
    ......@@ -214,6 +221,7 @@ begin -- behavioral
    rst_ext_n_i => rst_ext_n_i,
    rst_dmtd_n_i => rst_dmtd_n_i,
    clk_ref_i => clk_ref_i,
    clk_ref_sampled_i => clk_ref_sampled_i,
    clk_fb_i => clk_fb_i,
    clk_dmtd_i => clk_dmtd_i,
    clk_ext_i => clk_ext_i,
    ......@@ -239,11 +247,11 @@ begin -- behavioral
    wb_we_i => slave_i.we,
    wb_ack_o => slave_o.ack,
    wb_stall_o => slave_o.stall,
    wb_irq_o => int_o,
    irq_o => int_o,
    debug_o => debug_o,
    dbg_fifo_irq_o => dbg_fifo_irq_o);
    slave_o.err <= '0';
    slave_o.rty <= '0';
    end wrapper;
    modules/wr_tbi_phy/Manifest.py
    View file @ 486125a0
    files = [ "enc_8b10b.vhd",
    "dec_8b10b.vhd",
    "wr_tbi_phy.vhd",
    "disparity_gen_pkg.vhd" ];
    files = [ "enc_8b10b.vhd",
    "wr_tbi_phy.vhd",
    "disparity_gen_pkg.vhd" ];
    modules/wrc_core/wr_core.vhd
    View file @ 486125a0
    ......@@ -76,7 +76,7 @@ entity wr_core is
    g_simulation : integer := 0;
    -- set to false to reduce the number of information printed during simulation
    g_verbose : boolean := true;
    g_with_external_clock_input : boolean := true;
    g_with_external_clock_input : boolean := true;
    g_ram_address_space_size_kb : integer := 128;
    --
    g_board_name : string := "NA ";
    ......@@ -172,7 +172,7 @@ entity wr_core is
    phy_lpc_stat_i : in std_logic_vector(15 downto 0);
    phy_lpc_ctrl_o : out std_logic_vector(15 downto 0);
    -- PHY I/F record-based
    phy8_o : out t_phy_8bits_from_wrc;
    phy8_i : in t_phy_8bits_to_wrc := c_dummy_phy8_to_wrc;
    ......@@ -371,7 +371,7 @@ architecture struct of wr_core is
    return 0;
    end if;
    end f_to_integer;
    -----------------------------------------------------------------------------
    --Local resets for peripheral
    ......@@ -496,8 +496,8 @@ architecture struct of wr_core is
    signal cpu_dwb_out : t_wishbone_master_out;
    signal cpu_dwb_in : t_wishbone_master_in;
    signal ep_wb_in : t_wishbone_slave_in;
    signal ep_wb_out : t_wishbone_slave_out;
    ......@@ -844,7 +844,7 @@ begin
    wb_i => minic_wb_in,
    wb_o => minic_wb_out
    );
    U_CPU: entity work.wrc_urv_wrapper
    generic map (
    g_IRAM_SIZE => g_dpram_size,
    ......@@ -860,7 +860,7 @@ begin
    host_slave_i => cpu_csr_wb_in,
    host_slave_o => cpu_csr_wb_out
    );
    -----------------------------------------------------------------------------
    -- WB Peripherials
    -----------------------------------------------------------------------------
    ......@@ -994,7 +994,7 @@ begin
    cpu_csr_wb_in <= secbar_master_o(9);
    secbar_master_i(9) <= cpu_csr_wb_out;
    aux_adr_o <= secbar_master_o(10).adr;
    aux_dat_o <= secbar_master_o(10).dat;
    aux_sel_o <= secbar_master_o(10).sel;
    ......
    modules/wrc_core/wrc_periph.vhd
    View file @ 486125a0
    ......@@ -12,25 +12,25 @@
    -------------------------------------------------------------------------------
    -- Description:
    -- WRC_PERIPH integrates WRC_SYSCON, UART/VUART, 1-Wire Master, WRPC_DIAGS
    --
    --
    -------------------------------------------------------------------------------
    --
    -- Copyright (c) 2012 - 2017 CERN
    --
    -- This source file is free software; you can redistribute it
    -- and/or modify it under the terms of the GNU Lesser General
    -- Public License as published by the Free Software Foundation;
    -- either version 2.1 of the License, or (at your option) any
    -- later version.
    -- This source file is free software; you can redistribute it
    -- and/or modify it under the terms of the GNU Lesser General
    -- Public License as published by the Free Software Foundation;
    -- either version 2.1 of the License, or (at your option) any
    -- later version.
    --
    -- This source is distributed in the hope that it will be
    -- useful, but WITHOUT ANY WARRANTY; without even the implied
    -- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
    -- PURPOSE. See the GNU Lesser General Public License for more
    -- details.
    -- This source is distributed in the hope that it will be
    -- useful, but WITHOUT ANY WARRANTY; without even the implied
    -- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
    -- PURPOSE. See the GNU Lesser General Public License for more
    -- details.
    --
    -- You should have received a copy of the GNU Lesser General
    -- Public License along with this source; if not, download it
    -- You should have received a copy of the GNU Lesser General
    -- Public License along with this source; if not, download it
    -- from http://www.gnu.org/licenses/lgpl-2.1.html
    --
    -------------------------------------------------------------------------------
    ......@@ -135,7 +135,7 @@ architecture struct of wrc_periph is
    signal cntr_div : unsigned(23 downto 0);
    signal cntr_tics : unsigned(31 downto 0);
    signal cntr_overflow : std_logic;
    signal rst_wrc_n_o_reg : std_logic := '1';
    signal diag_adr : unsigned(15 downto 0);
    signal diag_dat : std_logic_vector(31 downto 0);
    ......@@ -144,8 +144,8 @@ architecture struct of wrc_periph is
    signal rst_net_n, rst_net_n_d0 : std_logic;
    signal rst_wrc_n, rst_wrc_n_d0 : std_logic;
    begin
    process(clk_sys_i)
    ......@@ -180,13 +180,13 @@ begin
    if(sysc_regs_o.rstr_trig_wr_o = '1' and sysc_regs_o.rstr_trig_o = x"deadbee") then
    rst_wrc_n <= not sysc_regs_o.rstr_rst_o;
    end if;
    end if;
    rst_net_n <= not sysc_regs_o.gpsr_net_rst_o;
    end if;
    end if;
    end if;
    end if;
    end process;
    -------------------------------------
    -- LEDs
    -------------------------------------
    ......
    modules/wrc_core/wrc_urv_wrapper.vhd
    View file @ 486125a0
    ......@@ -164,8 +164,6 @@ begin
    -- 1st MByte of the mem is the IRAM
    dm_is_wishbone <= '1' when dm_addr(31 downto 20) /= x"000" else '0';
    dm_data_write <= not dm_is_wishbone and dm_store;
    U_iram : generic_dpram
    generic map (
    g_DATA_WIDTH => 32,
    ......
    modules/wrc_core/xwr_core.vhd
    View file @ 486125a0
    ......@@ -11,10 +11,10 @@
    -- Standard : VHDL
    -------------------------------------------------------------------------------
    -- Description:
    -- WR PTP Core is a HDL module implementing a complete gigabit Ethernet
    -- interface (MAC + PCS + PHY) with integrated PTP slave ordinary clock
    -- compatible with White Rabbit protocol. It performs subnanosecond clock
    -- synchronization via WR protocol and also acts as an Ethernet "gateway",
    -- WR PTP Core is a HDL module implementing a complete gigabit Ethernet
    -- interface (MAC + PCS + PHY) with integrated PTP slave ordinary clock
    -- compatible with White Rabbit protocol. It performs subnanosecond clock
    -- synchronization via WR protocol and also acts as an Ethernet "gateway",
    -- providing access to TX/RX interfaces of the built-in WR MAC.
    --
    -- Starting from version 2.0 all modules are interconnected with pipelined
    ......@@ -25,20 +25,20 @@
    --
    -- Copyright (c) 2012 - 2017 CERN
    --
    -- This source file is free software; you can redistribute it
    -- and/or modify it under the terms of the GNU Lesser General
    -- Public License as published by the Free Software Foundation;
    -- either version 2.1 of the License, or (at your option) any
    -- later version.
    -- This source file is free software; you can redistribute it
    -- and/or modify it under the terms of the GNU Lesser General
    -- Public License as published by the Free Software Foundation;
    -- either version 2.1 of the License, or (at your option) any
    -- later version.
    --
    -- This source is distributed in the hope that it will be
    -- useful, but WITHOUT ANY WARRANTY; without even the implied
    -- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
    -- PURPOSE. See the GNU Lesser General Public License for more
    -- details.
    -- This source is distributed in the hope that it will be
    -- useful, but WITHOUT ANY WARRANTY; without even the implied
    -- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
    -- PURPOSE. See the GNU Lesser General Public License for more
    -- details.
    --
    -- You should have received a copy of the GNU Lesser General
    -- Public License along with this source; if not, download it
    -- You should have received a copy of the GNU Lesser General
    -- Public License along with this source; if not, download it
    -- from http://www.gnu.org/licenses/lgpl-2.1.html
    --
    -------------------------------------------------------------------------------
    ......@@ -70,7 +70,7 @@ use work.softpll_pkg.all;
    entity xwr_core is
    generic(
    --if set to 1, then blocks in PCS use smaller calibration counter to speed
    --if set to 1, then blocks in PCS use smaller calibration counter to speed
    --up simulation
    g_simulation : integer := 0;
    -- set to false to reduce the number of information printed during simulation
    ......@@ -181,7 +181,7 @@ entity xwr_core is
    phy8_i : in t_phy_8bits_to_wrc := c_dummy_phy8_to_wrc;
    phy16_o : out t_phy_16bits_from_wrc;
    phy16_i : in t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
    -----------------------------------------
    --GPIO
    -----------------------------------------
    ......@@ -440,7 +440,7 @@ begin
    abscal_txts_o => abscal_txts_o,
    abscal_rxts_o => abscal_rxts_o,
    fc_tx_pause_req_i => fc_tx_pause_req_i,
    fc_tx_pause_delay_i => fc_tx_pause_delay_i,
    fc_tx_pause_ready_o => fc_tx_pause_ready_o,
    ......
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