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White Rabbit core collection
Commit 486125a0 authored by A. Hahn's avatar A. Hahn
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merge: get current state from wrpc-v5 branch

parent 7dbca830
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    modules/wr_endpoint/wr_endpoint.vhd
    View file @ 486125a0
    ......@@ -1025,3 +1025,5 @@ begin
    gmii_tx_er_o <= '0';
    end syn;
    modules/wr_softpll_ng/wr_softpll_ng.vhd
    View file @ 486125a0
    This diff is collapsed.
    modules/wr_softpll_ng/xwr_softpll_ng.vhd
    View file @ 486125a0
    ......@@ -56,17 +56,15 @@ entity xwr_softpll_ng is
    -- These two are obvious:
    g_num_ref_inputs : integer := 1;
    g_num_outputs : integer := 1;
    -- Number of external channels (e.g. 2 for WR Switch for regular and low-jitter
    -- ext channel)
    g_num_exts : integer := 1;
    -- When true, an additional FIFO is instantiated, providing a realtime record
    -- of user-selectable SoftPLL parameters (e.g. tag values, phase error, DAC drive).
    -- These values can be read by "spll_dbg_proxy" daemon for further analysis.
    g_with_debug_fifo : boolean := false;
    -- When true, an additional accumulating bang-bang phase detector is instantiated
    -- for wideband locking of the local oscillator to an external stable reference
    -- (e.g. GPSDO/Cesium 10 MHz)
    g_with_ext_clock_input : boolean := false;
    -- When true, DDMTD inputs are reverse (so that the DDMTD offset clocks is
    -- being sampled by the measured clock). This is functionally equivalent to
    -- "direct" operation, but may improve FPGA timing/routability.
    ......@@ -79,6 +77,8 @@ entity xwr_softpll_ng is
    g_ref_clock_rate : integer := 125000000;
    g_ext_clock_rate : integer := 10000000;
    g_use_sampled_ref_clocks : boolean := false;
    g_interface_mode : t_wishbone_interface_mode := PIPELINED;
    g_address_granularity : t_wishbone_address_granularity := BYTE
    );
    ......@@ -92,17 +92,21 @@ entity xwr_softpll_ng is
    -- Reference inputs (i.e. the RX clocks recovered by the PHYs)
    clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
    -- Reference inputs (i.e. the RX clocks recovered by the PHYs), externally sampled
    clk_ref_sampled_i : in std_logic_vector(g_num_ref_inputs-1 downto 0) := (others => '0');
    -- Feedback clocks (i.e. the outputs of the main or aux oscillator)
    clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
    -- DMTD Offset clock
    clk_dmtd_i : in std_logic;
    -- External reference clock (e.g. 10 MHz from Cesium/GPSDO). Used only if
    -- g_with_ext_clock_input == true
    -- g_num_exts > 0
    clk_ext_i : in std_logic;
    -- External clock, multiplied to 125 MHz using the FPGA's PLL
    clk_ext_mul_i : in std_logic;
    clk_ext_mul_i : in std_logic_vector(f_nonzero_vector(g_num_exts)-1 downto 0);
    clk_ext_mul_locked_i : in std_logic := '1';
    clk_ext_stopped_i : in std_logic := '0';
    clk_ext_rst_o : out std_logic;
    ......@@ -144,12 +148,13 @@ architecture wrapper of xwr_softpll_ng is
    g_dac_bits : integer;
    g_num_ref_inputs : integer;
    g_num_outputs : integer;
    g_num_exts : integer;
    g_with_debug_fifo : boolean;
    g_with_ext_clock_input : boolean;
    g_reverse_dmtds : boolean;
    g_divide_input_by_2 : boolean;
    g_ref_clock_rate : integer;
    g_ext_clock_rate : integer;
    g_use_sampled_ref_clocks : boolean;
    g_interface_mode : t_wishbone_interface_mode;
    g_address_granularity : t_wishbone_address_granularity);
    port (
    ......@@ -159,10 +164,11 @@ architecture wrapper of xwr_softpll_ng is
    rst_ext_n_i : in std_logic;
    rst_dmtd_n_i : in std_logic;
    clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
    clk_ref_sampled_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
    clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
    clk_dmtd_i : in std_logic;
    clk_ext_i : in std_logic;
    clk_ext_mul_i : in std_logic;
    clk_ext_mul_i : in std_logic_vector(f_nonzero_vector(g_num_exts)-1 downto 0);
    clk_ext_mul_locked_i : in std_logic;
    clk_ext_stopped_i : in std_logic;
    clk_ext_rst_o : out std_logic;
    ......@@ -185,7 +191,7 @@ architecture wrapper of xwr_softpll_ng is
    wb_we_i : in std_logic;
    wb_ack_o : out std_logic;
    wb_stall_o : out std_logic;
    wb_irq_o : out std_logic;
    irq_o : out std_logic;
    debug_o : out std_logic_vector(5 downto 0);
    dbg_fifo_irq_o : out std_logic);
    end component;
    ......@@ -200,10 +206,11 @@ begin -- behavioral
    g_address_granularity => g_address_granularity,
    g_num_ref_inputs => g_num_ref_inputs,
    g_num_outputs => g_num_outputs,
    g_num_exts => g_num_exts,
    g_with_debug_fifo => g_with_debug_fifo,
    g_with_ext_clock_input => g_with_ext_clock_input,
    g_reverse_dmtds => g_reverse_dmtds,
    g_divide_input_by_2 => g_divide_input_by_2,
    g_use_sampled_ref_clocks => g_use_sampled_ref_clocks,
    g_ref_clock_rate => g_ref_clock_rate,
    g_ext_clock_rate => g_ext_clock_rate
    )
    ......@@ -214,6 +221,7 @@ begin -- behavioral
    rst_ext_n_i => rst_ext_n_i,
    rst_dmtd_n_i => rst_dmtd_n_i,
    clk_ref_i => clk_ref_i,
    clk_ref_sampled_i => clk_ref_sampled_i,
    clk_fb_i => clk_fb_i,
    clk_dmtd_i => clk_dmtd_i,
    clk_ext_i => clk_ext_i,
    ......@@ -239,7 +247,7 @@ begin -- behavioral
    wb_we_i => slave_i.we,
    wb_ack_o => slave_o.ack,
    wb_stall_o => slave_o.stall,
    wb_irq_o => int_o,
    irq_o => int_o,
    debug_o => debug_o,
    dbg_fifo_irq_o => dbg_fifo_irq_o);
    ......
    modules/wr_tbi_phy/Manifest.py
    View file @ 486125a0
    files = [ "enc_8b10b.vhd",
    "dec_8b10b.vhd",
    "wr_tbi_phy.vhd",
    "disparity_gen_pkg.vhd" ];
    modules/wrc_core/wrc_urv_wrapper.vhd
    View file @ 486125a0
    ......@@ -164,8 +164,6 @@ begin
    -- 1st MByte of the mem is the IRAM
    dm_is_wishbone <= '1' when dm_addr(31 downto 20) /= x"000" else '0';
    dm_data_write <= not dm_is_wishbone and dm_store;
    U_iram : generic_dpram
    generic map (
    g_DATA_WIDTH => 32,
    ......
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