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White Rabbit core collection
Commit 24a70af3 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Grzegorz Daniluk
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wr_gthe4_phyh_family7: last attempt to fix bitslide jumps before reverting to Xilinx's IP wrapper

parent 6936b1f3
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Showing with 8 additions and 3 deletions
platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_phy_family7.vhd
View file @ 24a70af3
...@@ -183,6 +183,8 @@ architecture rtl of wr_gthe4_phy_family7 is ...@@ -183,6 +183,8 @@ architecture rtl of wr_gthe4_phy_family7 is
signal tx_buffer_bypass_done : std_logic; signal tx_buffer_bypass_done : std_logic;
signal rx_buffer_bypass_done : std_logic; signal rx_buffer_bypass_done : std_logic;
signal rx_pcs_reset : std_logic;
function f_is_synthesis return boolean is function f_is_synthesis return boolean is
begin begin
-- synthesis translate_off -- synthesis translate_off
...@@ -241,7 +243,7 @@ begin ...@@ -241,7 +243,7 @@ begin
U_Bitslide : entity work.gtp_bitslide U_Bitslide : entity work.gtp_bitslide
generic map ( generic map (
g_simulation => g_simulation, g_simulation => g_simulation,
g_target => "virtex6") g_target => "ultrascale")
port map ( port map (
gtp_rst_i => rst_i, gtp_rst_i => rst_i,
gtp_rx_clk_i => RXUSRCLK2, gtp_rx_clk_i => RXUSRCLK2,
...@@ -249,7 +251,7 @@ begin ...@@ -249,7 +251,7 @@ begin
gtp_rx_byte_is_aligned_i => RXBYTEISALIGNED, gtp_rx_byte_is_aligned_i => RXBYTEISALIGNED,
serdes_ready_i => serdes_ready_rxusrclk, serdes_ready_i => serdes_ready_rxusrclk,
gtp_rx_slide_o => RXSLIDE, gtp_rx_slide_o => RXSLIDE,
gtp_rx_cdr_rst_o => open, gtp_rx_cdr_rst_o => rx_pcs_reset,
bitslide_o => rx_bitslide_o, bitslide_o => rx_bitslide_o,
synced_o => rx_synced); synced_o => rx_synced);
...@@ -412,6 +414,7 @@ begin ...@@ -412,6 +414,7 @@ begin
RXBYTEISALIGNED => RXBYTEISALIGNED, RXBYTEISALIGNED => RXBYTEISALIGNED,
RXCOMMADET => RXCOMMADET, RXCOMMADET => RXCOMMADET,
RXCTRL0 => RXCTRL0, RXCTRL0 => RXCTRL0,
RXPCSRESET => rx_pcs_reset,
rxctrl3 => rxctrl3, rxctrl3 => rxctrl3,
RXDATA => RXDATA, RXDATA => RXDATA,
RXOUTCLK => RXOUTCLK, RXOUTCLK => RXOUTCLK,
......
platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_wrapper.vhd
View file @ 24a70af3
...@@ -21,6 +21,8 @@ entity wr_gthe4_wrapper is ...@@ -21,6 +21,8 @@ entity wr_gthe4_wrapper is
TXRESETDONE : out std_logic; TXRESETDONE : out std_logic;
TXPROGDIVRESET : in std_logic; TXPROGDIVRESET : in std_logic;
RXPCSRESET : in std_logic;
GTHTXN : out std_logic; GTHTXN : out std_logic;
GTHTXP : out std_logic; GTHTXP : out std_logic;
...@@ -815,7 +817,7 @@ begin ...@@ -815,7 +817,7 @@ begin
RXOUTCLK => RXOUTCLK, RXOUTCLK => RXOUTCLK,
RXOUTCLKSEL => "010", RXOUTCLKSEL => "010",
RXPCOMMAALIGNEN => '0', RXPCOMMAALIGNEN => '0',
RXPCSRESET => '0', RXPCSRESET => RXPCSRESET,
RXPD => "00", RXPD => "00",
RXPHALIGN => '0', RXPHALIGN => '0',
RXPHALIGNDONE => RXPHALIGNDONE, RXPHALIGNDONE => RXPHALIGNDONE,
......
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