family7-gtx-lp lpdc via wishbone mdio

0c342bd3 · Peter Jansweijer · 816c0554 · 0c342bd3 · 0c342bd3
Commit 0c342bd3 authored Aug 21, 2023 by Peter Jansweijer
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Showing with 183 additions and 288 deletions

wr_gtx_phy_family7_lp.vhd ...ilinx/wr_gtp_phy/family7-gtx-lp/wr_gtx_phy_family7_lp.vhd +178 -284

wr_xilinx_pkg.vhd platform/xilinx/wr_xilinx_pkg.vhd +5 -4

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--- a/platform/xilinx/wr_gtp_phy/family7-gtx-lp/wr_gtx_phy_family7_lp.vhd
+++ b/platform/xilinx/wr_gtp_phy/family7-gtx-lp/wr_gtx_phy_family7_lp.vhd
--- a/platform/xilinx/wr_xilinx_pkg.vhd
+++ b/platform/xilinx/wr_xilinx_pkg.vhd
@@ -239,12 +239,13 @@ package wr_xilinx_pkg is
  component wr_gtx_phy_family7_lp is
  generic (
    -- set to non-zero value to speed up the simulation by reducing some delays
-    g_simulation     : integer := 0;
-    g_id             : integer := 0);
+    g_simulation     : integer := 0);
  port (
    clk_gtx_i        : in std_logic;
    clk_dmtd_i       : in std_logic;
    clk_ref_i        : in std_logic;
+    clk_sys_i        : in std_logic;
+    rst_sys_n_i      : in std_logic;
    tx_out_clk_o     : out std_logic;
    tx_locked_o      : out std_logic;
    tx_data_i        : in std_logic_vector(15 downto 0);
@@ -265,8 +266,8 @@ package wr_xilinx_pkg is
    pad_rxn_i        : in std_logic := '0';
    pad_rxp_i        : in std_logic := '0';
    rdy_o            : out std_logic;
-    lpc_ctrl_i       : in  std_logic_vector(15 downto 0) := x"0000";
-    lpc_stat_o       : out std_logic_vector(15 downto 0);
+    mdio_slave_i     : in  t_wishbone_slave_in;
+    mdio_slave_o     : out t_wishbone_slave_out;
    fmon_clk_tx_o    : out std_logic;
    fmon_clk_tx2_o   : out std_logic;
    fmon_clk_rx_o    : out std_logic);