endpoint/ep_rx_wb_master: select with generic if it should start cycle when stall is active

0aafd085 · Grzegorz Daniluk · 7955995d · 0aafd085 · 0aafd085
Commit 0aafd085 authored Jul 05, 2013 by Grzegorz Daniluk
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Showing with 13 additions and 5 deletions

ep_rx_path.vhd modules/wr_endpoint/ep_rx_path.vhd +2 -1

ep_rx_wb_master.vhd modules/wr_endpoint/ep_rx_wb_master.vhd +11 -4

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--- a/modules/wr_endpoint/ep_rx_path.vhd
+++ b/modules/wr_endpoint/ep_rx_path.vhd
@@ -203,7 +203,8 @@ architecture behavioral of ep_rx_path is

  component ep_rx_wb_master
    generic (
-      g_ignore_ack : boolean);
+      g_ignore_ack   : boolean;
+      g_cyc_on_stall : boolean := false);
    port (
      clk_sys_i  : in  std_logic;
      rst_n_i    : in  std_logic;

--- a/modules/wr_endpoint/ep_rx_wb_master.vhd
+++ b/modules/wr_endpoint/ep_rx_wb_master.vhd
@@ -31,7 +31,8 @@ use work.wr_fabric_pkg.all;

 entity ep_rx_wb_master is
  generic(
-    g_ignore_ack: boolean := true);
+    g_ignore_ack   : boolean := true;
+    g_cyc_on_stall : boolean := false);
  port (
    clk_sys_i : in std_logic;
    rst_n_i   : in std_logic;
@@ -62,7 +63,13 @@ architecture behavioral of ep_rx_wb_master is

 begin  -- behavioral
  
-  snk_dreq_o <= '1' when (src_wb_i.stall = '0' and state /= FINISH_CYCLE and snk_fab_i.eof = '0' and snk_fab_i.error = '0' and snk_fab_i.sof = '0' and enter_idle = '0') else '0';
+  gen_cyc_on_stall: if g_cyc_on_stall = true generate
+    snk_dreq_o <= '1' when ((src_wb_i.stall = '0' and state /= FINISH_CYCLE and snk_fab_i.eof = '0' and snk_fab_i.error = '0' and snk_fab_i.sof = '0' and enter_idle = '0') or state = IDLE) else '0';
+  end generate;
+
+  gen_nocyc_on_stall: if g_cyc_on_stall = false generate
+    snk_dreq_o <= '1' when (src_wb_i.stall = '0' and state /= FINISH_CYCLE and snk_fab_i.eof = '0' and snk_fab_i.error = '0' and snk_fab_i.sof = '0' and enter_idle = '0') else '0';
+  end generate;

  p_count_acks : process(clk_sys_i)
  begin
@@ -94,7 +101,7 @@ begin  -- behavioral
      else
        case state is
          when IDLE =>
-enter_idle <= '0';
+            enter_idle <= '0';
            src_out_int.adr <= snk_fab_i.addr;
            src_out_int.dat <= snk_fab_i.data;

@@ -115,7 +122,7 @@ enter_idle <= '0';

            if(src_wb_i.err = '1') then
              state <= IDLE;
-	    enter_idle <= '1';
+	            enter_idle <= '1';
              src_out_int.cyc <= '0';
              src_out_int.stb <= '0';
            elsif(snk_fab_i.error = '1') then