Skip to content
Snippets Groups Projects
Select Git revision
  • Fixed-latency-streamers
  • ML-sreamers-65.5MHz-Kintex7-ultrascale
  • ML-switchover-141015
  • ML-tmp-btrain-debug-v6
  • ML-tmp-debug-btrain
  • ML-tmp-virtex5_phy_resets
  • Mattia-ext-board-support
  • TRU-enabled-endpoint
  • TRU-enabled-endpoint-tmp
  • Virtex5_PHY_fix
  • WR-BTrain-PS-v2.1-based
  • adam-192k
  • adam-ci
  • bad_gtp_bitslide
  • cesar-160511-minic
  • cesar-pkt-cnt-09082017
  • cesar-pkt-cnt-sw-09082017
  • cesar_release_fix_170313
  • ci-test
  • cute-wr
  • wr-switch-sw-v8.0
  • wr-switch-sw-v7.0
  • wrpc-v5.0
  • wrpc-v5.0-pre1
  • fmc_adc_100m-v6.0.3
  • spec7_v4.2
  • wr-switch-sw-v6.0
  • btrain-v1.2
  • peter_spec7_v1
  • btrain-v2.5
  • wr-btrain-v1.1
  • wrpc-v4.2
  • wrpc-v4.1
  • wrpc-v4.0
  • wr-switch-sw-v5.0
  • wrpc-v3.0
  • wr-switch-sw-v4.2
  • wr-switch-sw-v4.0
  • wr-nic-v2.0
  • wrpc-v2.1
40 results
You can move around the graph by using the arrow keys.
Created with Raphaël 2.2.031Jul27241612111096326Jun531May232214230Apr2726252423201916131211229Mar282726201716131287528Feb2321171098625Jan24232221201918171612111014Dec13109130Nov292211654329Oct28272625241814630Sep22139525Aug232217151110329Jul2721201230Jun10931May1118Aprdefine platform dependent stuff only in syn/* Manifestwr_endpoint/wrc_core: moved t_txtsu_timestamp to endpoint's packageplatform/xilinx/wr_gtx_phy_virtex6: generic parameter for choice between global and regional clock buffers on RX clockwr_endpoint: revert to old RX CRC checking algorithm (suspect for RX errors)wr_softpll_ng: CRR_IN/CRR_OUT registers (counter sync) addedtiming/dmtd_with_deglitcher: added counter syncing across multiple DDMTDswr_pps_gen: use correct clock domain reset signalwr_mini_nic: partially fixed hang-on-RX-flood bugmodules/wr_endpoint: Tx timestamp strobe generation fixedwbp_mux: signals naming cleaned upExploder now works too. Wow that was easy to port.Remove unused signals from SCU top files.Fix timing for SCU2 (except DDR)Remove missing files from the SCU2 projectUpdate SCU2 project to use Etherbone package.Tom suggested this might be causing packet loss. It was!fixed wr aux clks, added new files to qsfFix Etherbone in SPEC!Bump LM32 memory to 90KB => improves timingsIncluded Etherbone into SPEC top design.modules/wr_endpoint: area optimizations in ep_rx_crc_size_checkConnect Etherbone config slave to the WRCDisconnect SFP1 pins, or else quartus will want them configured.Missing pin assignment: FPGA reset pinFix from Tom to increase the maximum filter program length.Copy changes from SCU2Fix the indentation of the SCU top file => remove tabs.fixed sfp i2c portfixed pll commentsEnable LM32 on power-upEnable LM32 debug interfaceMake the genum respect the Wishbone error line.Output driven twiceplatform/xilinx/wr_xilinx_pkg: removed use_refclk_out generics causing compliation errorswr_core: drive unused ack/err/rty wishbone signals to safe valuesMerge branch 'wishbonized' of ohwr.org:hdl-core-lib/wr-cores into wishbonizedwr_endpoint/ep_[tx/rx]_pcs_16bit: small fixes to infer FIFO18E1 on Virtex6wr_endpoint: re-generated WB slave, replaced VLAN/PFilter registers by RW/RW types which get synthesized away when not usedwr_endpoint/ep_clock_alignment_fifo: use HW-generated almost_empty flag instead of comparison of word counter with pass_threshold (less resources)Quartus project files for SCU2 didn't make it during merge