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Created with Raphaël 2.2.014Dec54325Nov23201916151411103130Oct29221916119230Sep29282625241917141331Aug302927232217630Jul29272618155329Jun1929May20Mar191622Feb1418Dec151413121186430Nov2431Oct6Sep25Aug18171610987Jul6430Jun262320191426May19164226Apr11523Mar17141310987632127Feb24232221201716143226Jan25242020Dec1924Nov23222117161483228Oct2726430Aug2624191727Jul261221Jun161312109876131May2426Apr222120158765131Mar2210712Feb815Jan15Dec14424Nov139529Oct201wr_board_pkg: declare eb_ethernet_slave as a component so that compiler doesn't complain when EB repo is not included Make cute_dp_core use xwrf interface, easy to connect with tcpip module.hm-cute-dp-oldhm-cute-dp-old Add simple dualport switch function.hdl: add auto-generated SDB meta info to SPEC and SVEC ref designssyn: remove Makefiles, they are auto-generated and contain paths that are not exportable to other users (such as the location of the Xilinx ISE tools)hdl: move Xilinx UCF files for SPEC and SVEC into the syn/ folder.hdl: bump general-cores, vme64x-core and gn4124-core to latest version in preparation for updating the SPEC and SVEC reference designsplatform/xilinx: replace PLLs with DCMs on Spartan-6board/svec: switch to new gc_reset_multi_aasd reset coreplatform/xilinx: Pass the 125MHz ref clock through the system clock PLL.wr_endpoint: remove chipscope used for preamble shrinkage update wrpc_sw bram/mif files for dualport. Add default value for signal rst_rxpath_n_i. Add special rst_rxpath_n_i signal for wr_endpoint. Add soft reset signal for endpoint and minic.Manifest: include only proper chipscope ngc depending on FPGA modelbin/wrpc: WRPC binary image for sis83ktom-streamerstom-streamerswr_streamers: added fixed latency diagnostic counter registers (timely/late/timed-out frames)wr_streamers: enable timeout handling & output statistics pulses in fixed_latency_delaywr_streamers: added timeout feature to fixed_latency_ts_matchmodules/timing: added synchronous pulse stamper module Correct the g_flash_secsz_kb to g_flash_secsz_KB.uplift general-coresMerge branch 'preamble_shrinkage' into proposed_masterboard/common: add fabric mode LOOPBACKwr_endpoint: add WB bit to generate preamble shrinkagepreamble cleanupadd rx preamble shrinkage support Add cute_dp_core generation project.streamers wiptom-sis83k-oct19tom-sis83k-oct19wr_1000basex_phy_model: fix in loopen_i pin handlingsim: trivial model of a 1000BaseX serdesupdated submodulestom-phaseboxtom-phaseboxwr_core: added missing generics/ports for the PhaseBoxwr_softpll_ng: fix post-merge error with the frequency meterspec_phasebox: eradicate dependency on Etherbonehdl: Eradicate INT from wishbone records and peripheral ports.wr_softpll_ng: extended clock frequency diagnostics to all input/feedback/ext/aux clockswr_softpll_ng: Enabled internal frequency reference for oscillator diagnosticsspec_phasebox: removed unnecessary WB crossbar