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Created with Raphaël 2.2.028Aug2013963231Jul27241612111096326Jun531May232214230Apr2726252423201916131211229Mar282726201716131287528Feb2321171098625Jan24232221201918171612111014Dec13109130Nov292211654329Oct28272625241814630Sep22139525Aug232217151110329Jul2721201230Jun10931May1118AprMerge branch 'master' of ohwr.org:hdl-core-lib/wr-coresmodules/wr_mini_nic: bugfixes to prevent WRPC from hanging on ping floodsim bugfix: default_xfer_size added to constructortop/spec_1_1/wr_core_demo: improved host- and host-less carrier reset, removed obsolete filesmodules/mini_bone: removed obsolete modulesim/softpll_regs_ng.vh: synced with latest VHDLsim/simdrv_defs.svh: added set_default_xfer_size() methodsim/simdrv_minic: driver for latest HDLplatform/xilinx/wr_gtp_phy_spartan6: added generic for enabling/disabling GTP channels (saves logic/BUFG resources on unused channels)pps_gen: separate 1-pps output to drive DIO ledwrpc-v2.0wrpc-v2.0tricks and constraints so that the deltaTx/Rx calibration is not necessary for every synthesized WRPC bitstreamspec_top: turn on vuart in wrpcBackport the scu2 design to the pexariawrc_syscon: updated wb slave interface with latest wbgenwr_mini_nic: updated wb slave interface with latest wbgenClean up the reset logic for the GSI top filesremoved old softpll corespec_top: modelsim does not like or-ing signals inside componentdefine platform dependent stuff only in syn/* Manifestwr_endpoint/wrc_core: moved t_txtsu_timestamp to endpoint's packageplatform/xilinx/wr_gtx_phy_virtex6: generic parameter for choice between global and regional clock buffers on RX clockwr_endpoint: revert to old RX CRC checking algorithm (suspect for RX errors)wr_softpll_ng: CRR_IN/CRR_OUT registers (counter sync) addedtiming/dmtd_with_deglitcher: added counter syncing across multiple DDMTDswr_pps_gen: use correct clock domain reset signalwr_mini_nic: partially fixed hang-on-RX-flood bugmodules/wr_endpoint: Tx timestamp strobe generation fixedwbp_mux: signals naming cleaned upExploder now works too. Wow that was easy to port.Remove unused signals from SCU top files.Fix timing for SCU2 (except DDR)Remove missing files from the SCU2 projectUpdate SCU2 project to use Etherbone package.Tom suggested this might be causing packet loss. It was!fixed wr aux clks, added new files to qsfFix Etherbone in SPEC!Bump LM32 memory to 90KB => improves timingsIncluded Etherbone into SPEC top design.modules/wr_endpoint: area optimizations in ep_rx_crc_size_checkConnect Etherbone config slave to the WRC