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Created with Raphaël 2.2.02Sep131Aug14114323Jul14319May1325Mar221713Feb11105426Jan14139823Dec94128Nov17141210931Oct271524Jul221724Jun2318171222May191612828Apr1574327Mar262419181376520Feb1476431Jan302928161323Dec20166229Nov26191715141312876128Oct2523427Sep2623171611109853230Aug28272623222116145229Jul262522520Jun19181312422May159730Apr2926252423191710525Mar2221201918151413128754128Feb272519181413121110817Jan20Dec181714121165428Nov2322212016updating gn4124-core for v2.0update general-cores to current proposed_masterspec_top: removing old constraintwr_endpoint: trivial build_wb.sh fix to generate also mdio header filerst_n_rx_i both U_Rx_Clock_Align_FIFO and U_match_buffer in parallelmodules/endpoint: adding MDIO ECTRL registeradded delta delays in phy output signals to line up with the ch#_rx_rbclk_o assignment (purely necessary for proper simulation only)when oob.valid, ep_tx_pcs_16bit should (just as ep_tx_psc_8bit) wait for the U_TX_FIFO to empty in order to catch the proper timestamp for the oob signalled packet.platform/wr_xilinx_pkg: fixing Kintex-7 GTX component declarationplatform/gtp: adding PRBS generator inputswrc_core: bubble up tx pause control signalswrc_core: improve 8/16-bit PCS selectioninit value for wr-core uart_rxd_i set to '1'fixed double driver for signal debug_o(4)modules: regenerate wishbone Slave interfaces with updated wbgenwr-pstats-node: typo in signal declarationwr-pstats-nodewr-pstats-nodewr-pstats-node: add overflow lines and rst of counters for dbgwr-pstats-node: redesign of the pstatswr_pstats: rename the module wrsw_pstatswr-pstats: merge with proposed_masterspec_top: wire sfp tx_fault/los/tx_disable signals to the wr coreplatform/xilinx: adding detailed loopback vector to GTPwr_endpoint: keep also 1-bit loopback signal for PHYs that don't accept detailed vectoradded tx_prbs_sel, sfp_tx_disable, sfp_loss, sfp_tx_fault and full width loopback to MDIO Control register. Be careful: Single bit loopback was relocated to accomodate loopback(2:0)!added full width loopen_i, tx_prbs_sel_i and tx_locked_o portswr_core: disabled debugging in LM32 to improve timingmodules/wr_softpll_ng: for ext channel, use locked signal to notify lm32 if 10mhz in is therewr-switch-sw-v4.2wr-switch-sw-v4.2modules/wr_eca: trivial, move package file to the top of the Manifest filemodules/endpoint: count rx frames at the end of rx_path chain and let wr_endpoint decide which one to exportmodules/wr_endpoint: add input to stop RX traffic (for WRS watchdog)wr_endpoint: don't make RTU request when frame was not stored in the rx bufferwr_core: updating the core and a reference design to feed phy_rdy_i of the endpointwr_endpoint: keep rx pcs and rx clk alignment fifo in reset until serdes is lockedwr_endpoint: clean-up components declarations, remove duplicates, move them to a private packageplatform/xilinx: adding rdy_o to gtx and gtp wrappers to indicate when serdes is ready and produces rx clockendpoint: record-based debug for chipscopetop/virtex5_kit: demo for Xilinx ML605 kit (no timing yet, but link is up)tom-virtex5-sup…tom-virtex5-supportplatform/xilinx: initial support for Virtex5 GTP transceiverwr_core: pass g_simulation to the WR endpointv5 -> platform manifest