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Created with Raphaël 2.2.020Jan171617Dec1196225Nov191211130Oct242321181425Sep30Aug2920139830Jun272621191413121165431May2827252423222120161413109730Apr26231129Mar2827251211876528Feb261631Jan2823222114Dec54325Nov23201916151411103130Oct29221916119230Sep29282625241917141331Aug302927232217630Jul29272618155329Jun1929May20Mar191622Feb1418Dec151413121186430Nov2431Oct6Sep25Aug18171610987Jul6430Jun262320191426May19164226Apr11523Mar171413109wr_endpoint: don't reset the endpoint on LOS! - it breaks LPDCwr_softpll_ng: removed int signaleca_wb_event.vhd: removed int signalwrc_core: solved merge conflictsMerge branch 'wr_starting_kit_update' into proposed_masterwr_nic_wrapper: Fix indentation.sim: Add VIC registers file for simulation.spec: Changes for the SPEC board block.wr_nic_wrapper: Add NIC wrapper block code.wrc_core: Export PPS valid output port.svec7: bring back PLL aux clock, pll reference is 125 MHztom-svec7-teststom-svec7-testslow phase drift: add RX synchronizerboard: initial support for Xilinx ZCU106 devkittom-gthe4-zynqu…tom-gthe4-zynqultrascaleplatform/xilinx: wrapper for Zynq Ulrascale+ GTHE4 transceiverboard: added template files for an Artix version of SVEC7xwrc_board: disable the blooody Etherbone core instantiation, adds a useless dependency!tom-dec03tom-dec03fixed confilctspascal_kc705pascal_kc705removed absolute pathsadded pcie functionalityfixed bug of swapped i2c linesin sfpinitial commit of the kc705/RabbitFX fileswr_gtx_phy_virtex6_lp: Tom's adding chicken bits...merge: arria 10 gsi wr-v4.2merge: gsi wr-v4.2arria10: added html files to .gitignorewrpc-v4.2_gsi_a…wrpc-v4.2_gsi_a10_cleanuparria10: removed html filesarria10: cleaned up autogenerated filesarria10: simplified phy HDL and Manifest.pyarria10: simplified folder structurearria10: removed auto-generated and temp filesFixed typowr_arria10_scu4_phy: added *.cmp to .gitignorewr_arria10_e3p1_phy: added *.cmp to .gitignorewr_arria10_e3p1_phy: added .gitignorewr_arria10_scu4_phy: added .gitignorearria10: scu4 -> removed autogenerated files (plls and phy)arria10: e3p1 -> removed autogenerated files (plls and phy)arria10: e3p1 -> updated atx_pll and cmu_pll and phy change ext_clk to clk_10m_ext_o.hm-cute-dphm-cute-dpboard/svec7: initial version