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Created with Raphaël 2.2.011Mar7528Feb212019181330Jan29222017141317Dec13528Nov26252018151413118730Oct28972126Sep24232010930Aug2921129824Jul1725Jun18135331May29109215Apr14419Mar1427Feb2320525Jan1020Dec191211729Nov24109623Oct18Sep65431Aug3029251721Jul201917137323Jun221614129754230May2322171195228Apr2625211812331Mar15148224Feb25Jan122Dec121Nov171143131Oct25May231813Apr1211831Mar29282214111015Feb11327Jan10Dec926Oct151215Sep78Jul25Jun217May5422Apr1915141224Mar15141210819Feb18171426Jan18128615Dec10987513Nov6226Oct229Sep2221181615Add phy for agilex7pcie400pcie400Use single clock dpram in ep_packet_filterExport disparity flag in dec_8b10bUse parameter instead of fixed valueidrogen-develop…idrogen-develop idrogen-wrpc-125mamd-devboard: Swap address of gnss uart with Si570mle/upstream/zc…mle/upstream/zcu10x_gnsszcu10x: Add GNSS uart supportAdd options for 125MHz WRCMerge commit eb19e1dbwrpc-v5-idrogen…wrpc-v5-idrogen-mergeUpdate vme64x-core to mastermastermasterUpdate urv-core submoduleUpdate gn412-core to masterUpdate general-cores submodule to masternmea: update checksum generation, ignore $ and * delimitershl-wrpc-v5.0hl-wrpc-v5.0spll add channels for holdover clks and add exp board gpio interfacewrs-v4-devwrs-v4-devZCU10x: Add HPC1 support for XM105mle/upstream/zc…mle/upstream/zcu102zcu10x: Add hw fmc enable signalzcu106: Rudimentary ZCU106 buildZCU10x: Remove unused QPLL, ex "main"platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_sdm_*: remove duplicate common IP files for GTH w/ SDM for Light Rabbit, since they already exist in platform/xilinx/wr_gtp_phy/xilinx-ip/common; update Manifest.py accordinglyplatform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_sdm_eth/gtwizard_v1_7_gthe4_sdm_eth.tcl: fix IP generation, update location to SFP2 (matching ZCU102 board constraints)zcu102_ref_design: Update readme, remove fsbl patchzcu102_ref_design: remove sfp_los_i input, change clk_sys to std_logicxwrc_platform_vivado: Reset dmtd and main clk during phy resetzcu102: Add Si570 module for de-tuning the DMTD clock through tertiary (aux) crossbarplatform/xilinx/xwrc_platform_vivado.vhd: De-couple sys clk from main/ref clkzcu102_ref_design: remove sfp_det_i inputzcu102_ref_define/Manifest.py: fix the partxwrc_board_zcu102: negate sfp_tx_disablezcu102: Update .bram file with correct I2C-mux setting for SFP modulezcu102: Add fsbl.patch file to syn folder for zcu102/amddevboardzcu102_ref_design: Add reference design for ZCU102platform/xilinx: Add input signals for PLL DAC valuesmodules/wrc_core/Manifest.py: Add dependency on urv-coreFix minor misspelling in testbench print messageMerge branch 'idrogen-develop' into 'wrpc-v5-idrogen-merge'Add idrogen dmtd pllRemove Arria10 PLL script to generate at project levelMerge branch 'hl-wr-switch-sw-v8' into 'master'Revert "virtex6 use phy from wr-switch-sw-v7.0"virtex6 use phy from wr-switch-sw-v7.0wr-switch-sw-v8.0wr-switch-sw-v8.0