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Created with Raphaël 2.2.04Feb31Jan302928161323Dec20166229Nov26191715141312876128Oct2523427Sep2623171611109853230Aug28272623222116145229Jul262522520Jun19181312422May159730Apr2926252423191710525Mar2221201918151413128754128Feb272519181413121110817Jan20Dec181714121165428Nov2322212016158731Oct292519168227Sep20121110330Aug282013963231Jul27241612111096326Jun531May232214230Apr27262524232019161312112evaluating two possible solutions (some optimization), both in the code, one commented outenabled dreq on SOFgeneric to enable/disable early_addr_match, disabled by default (at least now)bypass fifo included directly into the CRC module to optimize for speed (2 cycles now) and resources (can use standard fifo)reverted one optimization (did not work for tagging) and made another optimization - starts passing the data at the last cycle of INSERT_TAG - saved cycleset generic of rx_wb_master g_cyc_on_stall to TRUE in order to save some cycles at the datat transferoptimized by 1 cyclehack-fix of tx_pcs FIFO - it was >hiding< frames somehow causing the latency for frames with even size to increase from <3 to ~18us - the temporary solution is to use v6_hwfifo which takes more resourcesadded loads of stuff to debug (with chipcscope) endpoint in the switch - the commit potentially to remove when cleaningadded some chipscope'ing stuff (commented out by default, to be easily used)optimized by decreasing tx_itf_gap hardcoded in FSM, parametrized thishandling of situation when SOF and EOF are in the same cycle -- it prevented RTU request from being made and SWcore to go nutsoptimized to start CRC check as soon as OOB received (taking advantage of fab.addr propagaton through fab_pipe added in prev commit), adding proper fab.addr propagation further downpropagating fab.addr through fab_pipe so thattx_crc_inserter module can detect OOB (and not wait for EOF)optimized by making default generic to prevent syntezising stuff which is normally not used (hp detection)optimized the way CRC is flushed (including bypass_queue - solution which takes more resources)optimized by shortening the dreq_o masking (only for 1-cyc before status is inserted)optimized not to make 1-cycle stall when going though ethertype of non-Q-taggged frameEndpoint: adding new PSTATs vectors to endpoint -- for each classEndpoint: assiging 0 class to undatgged framewr_endpoint: added new signal/trigger to endpoints RMONs (PSTATS)Endpoint: bugfix in rx, when tagging, the before-tagging VID was passed to RTUEndpoint: bugfix in tx untagging - VLAN tag layout/interpretation correctiongreg_counters: connect rx pclass eventsEndpoint: bugfix of procedure for PSTATSgreg_counters: add tx/rx frame event to the rmon recordgreg_counters: use constant instead of fixed size of events generated by endpointgreg_counters: add generation of event per rx pclassEndpoint-PAUSE: changing naming of 802.3 pause in WB regs so that it's compatible with old versionsgreg_counters: add tx, rx event generation for each sent/received framegreg_counters: output all rmon events from endpoint componentgreg_counters: make rmon of PCS output only (not inout anymore)greg_counters: make rmon of ep_rx_path outputs only (not inout anymore)greg_counters: leave rmon_o from vlan unit open, it doesn't generate any eventsgreg_counters: events from rx_status_reg_insert blockgreg_counters: move rx_pause event outside rx status reg insert blockgreg_counters: events from rx crc size checkgreg_counters: tx pcs events outputted and aligned with clk_sysgreg_counters: rx pcs events outputted and aligned with clk_sysEndpoint-RX_PAUSE: changing configuration to allow enabling both kinds of PAUSE (802.3 and 802.1Q), fixing bug for 802.3 - remembering wrong quanta