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Created with Raphaël 2.2.030Aug2920139830Jun272621191413121165431May2827252423222120161413109730Apr26231129Mar2827251211876528Feb261631Jan2823222114Dec54325Nov23201916151411103130Oct29221916119230Sep29282625241917141331Aug302927232217630Jul29272618155329Jun1929May20Mar191622Feb1418Dec151413121186430Nov2431Oct6Sep25Aug18171610987Jul6430Jun262320191426May19164226Apr11523Mar17141310987632127Feb24232221updated .gitignorewr_gtx_phy_virtex6_lp: fix early link detection failure during autonegotiationwr_gtx_phy_lp: fixed early link detection FSMplatform: added low phase drift GTX PHY for Virtex6wr_softpll_ng: connect unused clk_sampled_i inputs to 0wr_softpll_ng: added support for external DDMTD samplerwr_endpoint: added MDIO debug registers and corresponding PHY portstiming: added external sampling option to dmtd_with_deglitchertiming: added a bare DMTD sampler moduleFix OHWR repo URLs.klyone-180419-f…klyone-180419-finedel_fixesMerge branch 'greg-wrs-low-jitter' into proposed_masterwr_softpll: number of ext channels specified with generic add cute dp core projet file. add cute core project file.hm-cutehm-cutexwr_softpll: add ext low jitter board genericsoftpll ljd: fix tag index to enable regular ext channelAdded support for the external board remove debug interfaces for easy compilation.hm-wrslj-ptshm-wrslj-ptskintex7-lp: stuck on losing-the-2nd-word issue, going back to 1.25 native tx pathupdated submoduleswr_arria10_e3p1_atx_pll: changed output frequency (fcmu = fatx)wrpc-v4.2_gsi_a10wrpc-v4.2_gsi_a10platform: wr_arria10_e3p1_phy.tcl added cmu pll ip corewr_arria10_e3p1_det_phy: changed input frequency (to match CMU PLL)platform: added cmu pll for arria 10wr_gtx_phy_kintex7_lp: fixed DMTD configuration to match new clock frequencies, more control over resetswrc_core: increase AUX address space to 32 kB in SDB descriptordmtd_sampler: initialize clock divider flip-flop, added to Manifestwr_gtx_phy_kintex7_lp: wippps_gen: fix adjustment status bit description to match implementationwr_gtx_phy_kintex7_lp: gave up with RX oversampling...wr_endpoint/wr_core: independent 8/16-bit PCS data path selection (WIP)kintex7-lp: WIP on oversampled version, not sure if it will be needed with the QPLLUpdated softpll interface to integrate new switch lj componentsMerge remote-tracking branch 'origin/hm-wrsfl' into hm-wrslj-pts update .gitmodules url.kintex7_lp: hacking oversampled version of the transceiverpps_gen: add bit to control WRS 1-PPS in termination - required for WRSMerge branch 'wrpc-v4.2_gsi' of ssh://ohwr.org:7999/project/wr-cores into wrpc-v4.1_a10modules: added decoder to Manifest.pywrpc-v4.2_gsiwrpc-v4.2_gsifix simulation for hdlmake-v3.2