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Created with Raphaël 2.2.020Dec181714121165428Nov2322212016158731Oct292519168227Sep20121110330Aug282013963231Jul27241612111096326Jun531May232214230Apr2726252423201916131211229Mar282726201716131287528Feb2321171098625Jan24232221201918171612111014Dec13109130Nov292211654329Oct28272625241814630Sep22139525Aug232217151110329Jul2721201230Jun10931May1118Aprchanging build_wb.sh, removing paths to wbgen2adding platform to manifestendpoint: small bugfixes in injection module and tx header processor + adding missing description to wbgen fileroot Manifest: add platform subdirectoryhdlmake-testshdlmake-testsbugfix in eth packet simulation class. It was not possible to set pck size at initialization (new function) -- bug fixedEndpoint: bugfix in h/w pck injection. The EOF signal generated when injecting h/w pck was not passed on the fabric.Endpoint-pfilter: nasty bug fix. Done by hand according to Toms patch, commit to be skipped when rebasingEndpoint-pfilter: adding Packet Filter microcode SystemVerilog class by Tom. It is used to program the endpoint pakcet filterEndpoint-VLANs: fixing VLAN related stuff in the rx_path of endpoint. Enabling RTU_header_extraction for VLAN-tagged frames. Fixing bug related with wrong order in VLAN-tag. Correcting VLAN-tag insertion.wr_endpoint/ep_packet_filter.vhd: compare word fetch bugfix [CRITICAL]fabric/xwb_fabric_source: allow for sof right after eof of previous frametop/spec_1_1/wr_core_demo: improved host- and host-less carrier reset, removed obsolete filesmodules/mini_bone: removed obsolete moduletop/spec_1_1/wr_core_demo: fix I2C/DIO pin assignmenttom-softpll-gen…tom-softpll-genericizedtestbench: trival TB for Si57x interfacewrc_core/si570_if: I2C register layout fixes, freeze the RFREQ before updatingwr_softpll_ng/softpll_pkg.vhd: default BB channel setting for Si57x running at 100 MHzwr_softpll_ng: disable PPS resyncing on BB-based aux channels (to be reworked)endpoint: VLANs related bugfix. Adding extraction of VLAN-tag related info to the rtu_header_extract and correcting VLAN-related packet tx/rx simulation (there was wrong order of VLAN-tag)TRU-related fix: making sure that killing/reviving link in the middle of tx of frame is handled properly by Endpoint (hackish)top/spec_1_1/wr_core_demo: test top level for disciplining Si570 oscillatorplatform/xilinx: added Chipscope by defaultManifest.py: add platform and disable GSI modules stuff by defaultwr_core: interface for si570 oscillator (untested)wr_core: propagate generics of the genericized softpllwr_softpll_ng: added choice between DDMTD or bang-bang phase detector on each output channelendpoint: changes ported from TRU branch to integrate killing of portssim: packet sink: commenting disturbing display()sim: bugfix in wishbone accessor. The bug prevented from sending packetsTRU: adding features and I/F necessary for TRU unit. I/F for packet filter, flow ctr and adding functionality for killing linktestbench/xwrf_mux: correct masksfabric/xwrf_mux: forward packet to first matching interfacepacket sink simulation: making the output more readible by removing display()trutruwrc_core/wr_core: fix mux class assignment, they are masks, not IDsfabric/xwrf_mux: cleaner mask/target filtering functionwrc_core/wrcore_pkg: expose g_aux_sdb in xwr_core component declarationfabric/xwb_fabric_source: raise CYC when STALL is high (fixes freeze with the new wbp_mux)removed unused includeswrc_core/wrcore_pkg: expose g_aux_sdb in xwr_core component declarationtom-endpoint-in…tom-endpoint-injection-vlansfabric/xwb_fabric_source: raise CYC when STALL is high (fixes freeze with the new wbp_mux)