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Created with Raphaël 2.2.08Dec7513Nov6226Oct229Sep22211816151411974331Aug272625212017765431Jul29281716963126Jun2523221228May191413128729Apr2725232221149873127Mar201124Feb2120731Jan30282120171617Dec1196225Nov191211130Oct242321181425Sep30Aug2920139830Jun272621191413121165431May2827252423222120161413109730Apr26231129Mar2827251211876528Feb261631Jan2823222114Dec543sim: add raw mode to the serdes modelvirtex5: bypass internal PHY 8b10b decoder + improved alignment detect/resettom-dec07tom-dec07sim: add raw mode to the serdes model[PHY/Virtex5] synchronize resets with rx_clkML-tmp-virtex5_…ML-tmp-virtex5_phy_resetsmore LM32 memory for software developmentgreg-256kgreg-256kmore LM32 memory for software developmentadam-192kadam-192kplatform/xilinx/wr_gtp_phy: added Vivado-generated wrapper files for GTHE3tom-nov06tom-nov06updated designwr_core: added generic to select LM32 RAM address space size (128/256 kB). Default = 128 kBtom-nov02tom-nov02wr_core/softpll_ng: fixed irq buggsi_master_get_…gsi_master_get_back_on_track_oct2020_softpll_fixwr_gtx_phy_family7: made clock buffers optional through generictom-svec7tom-svec7update general-cores to fix vuartspec,svec top: remove sdb and remap WRPC at 0x0wrc_core: swap aux WB and diags in secondary crossbarRepaired wrc_core memory map comment (due to Toms commit 3e433e2 "wrc_core: increase LM32 code/data address space to 256 kB")peter_spec7_v5 …peter_spec7_v5 proposed_spec7_v5Added processing system to ref design.repaired pll_clk_sel_o being invertedspec7_v4.2 prop…spec7_v4.2 proposed_spec7Splitted the tx_timestamp signal in two clock domains; refclk for phys output, sysclk for lm32Splitted the tx_timestamp signal in two clock domains; refclk for phys output, sysclk for lm32platform/xilinx: select appropriate platform based on the FPGA family, not synthesis toolCI: add pxie_ref_design vivado synthesisplatform/xilinx: split platform for vivado to a separate file not to break ise build with unknown primitivesboard/spec: fix async reset bug introduced in commit 1077235adding LM32 binary for PXIe FMC carrier with ZU7board/pxie-fmc: adding std_logic wrapperadding BSP for PXIe-FMC board with Xilinx ZU7platform/xilinx: adding support for Zynq US+platform/xilinx: global clk_sys signal declaration so that it's available between generate blocksplatform/xilinx: remove unnecesary files for Ultrascale familymodules/wrc_core: bring back link_ok_o functionalityplatform/xilinx: Manifest indentation fix, no technical changeplatform/xilinx: revert to Vivado-generated wrapper for GTHE3wr_gthe3_phy_family7: reset RX PCS after link loss to ensure reset of the bitslide counterwr_gthe3_phy_family7: possible fix for failing link up detection after disconnecting the fiberwr_gthe3_phy_family7: assert rx_enc_err when the link is down to reliably force link down event in the PCSwr_core: expose UART FIFO configuration to wr_core genericswrc_core: expose PHY LPC interfaceplatform: pre-validated version of kintex-7 lpdc phywrc_core: increase LM32 code/data address space to 256 kBwr_softpll_ng: expose g_with_debug_fifo bit through Wishbone