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Created with Raphaël 2.2.021Sep1816151411974331Aug272625212017765431Jul29281716963126Jun2523221228May191413128729Apr2725232221149873127Mar201124Feb2120731Jan30282120171617Dec1196225Nov191211130Oct242321181425Sep30Aug2920139830Jun272621191413121165431May2827252423222120161413109730Apr26231129Mar2827251211876528Feb261631Jan2823222114Dec54325Nov232019repaired pll_clk_sel_o being invertedspec7_v4.2 prop…spec7_v4.2 proposed_spec7Splitted the tx_timestamp signal in two clock domains; refclk for phys output, sysclk for lm32Splitted the tx_timestamp signal in two clock domains; refclk for phys output, sysclk for lm32platform/xilinx: select appropriate platform based on the FPGA family, not synthesis toolCI: add pxie_ref_design vivado synthesisplatform/xilinx: split platform for vivado to a separate file not to break ise build with unknown primitivesboard/spec: fix async reset bug introduced in commit 1077235adding LM32 binary for PXIe FMC carrier with ZU7board/pxie-fmc: adding std_logic wrapperadding BSP for PXIe-FMC board with Xilinx ZU7platform/xilinx: adding support for Zynq US+platform/xilinx: global clk_sys signal declaration so that it's available between generate blocksplatform/xilinx: remove unnecesary files for Ultrascale familymodules/wrc_core: bring back link_ok_o functionalityplatform/xilinx: Manifest indentation fix, no technical changeplatform/xilinx: revert to Vivado-generated wrapper for GTHE3wr_gthe3_phy_family7: reset RX PCS after link loss to ensure reset of the bitslide counterwr_gthe3_phy_family7: possible fix for failing link up detection after disconnecting the fiberwr_gthe3_phy_family7: assert rx_enc_err when the link is down to reliably force link down event in the PCSwr_core: expose UART FIFO configuration to wr_core genericswrc_core: expose PHY LPC interfaceplatform: pre-validated version of kintex-7 lpdc phywrc_core: increase LM32 code/data address space to 256 kBwr_softpll_ng: expose g_with_debug_fifo bit through Wishbonekintex7-lp: stuck on losing-the-2nd-word issue, going back to 1.25 native tx pathwr_gtx_phy_kintex7_lp: fixed DMTD configuration to match new clock frequencies, more control over resetswrc_core: increase AUX address space to 32 kB in SDB descriptordmtd_sampler: initialize clock divider flip-flop, added to Manifestwr_gtx_phy_kintex7_lp: wipwr_gtx_phy_kintex7_lp: gave up with RX oversampling...kintex7-lp: WIP on oversampled version, not sure if it will be needed with the QPLLkintex7_lp: hacking oversampled version of the transceiverwr_softpll_ng: Enabled internal frequency reference for oscillator diagnosticswr_gtx_phy_kintex7_lp: removed some unused signalswr_core: expose SoftPLL's g_use_sampled_ref_clocks generic & associated interfacewr_softpll_ng: added support for external DDMTD samplerplatform: phase-stable GTXE2 wrapper (Kintex7), initial versionplatform: hacking the GTXE2 wrapperwr_core: extend aux address space to 32kBsim/8b10b_encoder: fix logic signal aliasing with a port