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Created with Raphaël 2.2.015Dec14424Nov139529Oct20128Sep2131Aug14114323Jul14319May1325Mar221713Feb11105426Jan14139823Dec94128Nov17141210931Oct271524Jul221724Jun2318171222May191612828Apr1574327Mar262419181376520Feb1476431Jan302928161323Dec20166229Nov26191715141312876128Oct2523427Sep2623171611109853230Aug28272623222116145229Jul262522520Jun19181312422May159730Apr2926252423191710525Mar2221201918151413128754128Feb272519181413121110817Jan20Dec18171412116xilinx/wr_gtp_phy: remove not existing file from the ManifestMerge branch 'proposed_master'wrpc: update synthesis Manifest for new hdlmakewrpc: trivial fix to commit e38dff8, I forgot one genericwrpc: set default generics for users who use wrpc in their own designsMerge branch 'proposed_master'spec/wrc.ram: update to 2a791f3 wrpc-sw buildsoftpll: update build_wb.sh so that also doc is generatedext pll: for spartan use clk_in stopped indicator and reset signaletherbone: update submodule, now workinggsi_test_stabil…gsi_test_stability_24112015gsi_siox : adapt pin assignment for the gsi fmcspec/wrc.ram: update to 5ab76f6 wrpc-sw buildaltera: move gsi-specific PLLs to bel_projectsgsi_stability_t…gsi_stability_test_241115spec/wrc.ram: update to 67a039a wrpc-sw buildkintex-7 reference design updated such that it can do grand-master mode (putting the DIO card on the CLB FMC connector and inputting 10 MHz and PPS).update wrpc testbenchupdate wrc.ramsim: fix simulation models and driversmodules/fabric: adding xwrf_loopback module for testing WRPC with network testerupdate submoduleswr_mini_nic: go through RX_MEM_FLUSH only when neededremoving old README filesadd Kintex7 reference design ucf fileSet output enable of testpads always activeadded knitex7 reference design fileswrc_core: set g_ref_clock_rate based on pcs 8/16bit widthupdating gn4124-core for v2.0update general-cores to current proposed_masterspec_top: removing old constraintwr_endpoint: trivial build_wb.sh fix to generate also mdio header filerst_n_rx_i both U_Rx_Clock_Align_FIFO and U_match_buffer in parallelmodules/endpoint: adding MDIO ECTRL registeradded delta delays in phy output signals to line up with the ch#_rx_rbclk_o assignment (purely necessary for proper simulation only)when oob.valid, ep_tx_pcs_16bit should (just as ep_tx_psc_8bit) wait for the U_TX_FIFO to empty in order to catch the proper timestamp for the oob signalled packet.platform/wr_xilinx_pkg: fixing Kintex-7 GTX component declarationplatform/gtp: adding PRBS generator inputswrc_core: bubble up tx pause control signalswrc_core: improve 8/16-bit PCS selectioninit value for wr-core uart_rxd_i set to '1'fixed double driver for signal debug_o(4)