keep endpoint fifos in reset until serdes is locked
Earlier we were resetting clock alignment fifo (ep_rx_path) when
serdes was still
not locked and was not producing rx clock. Xilinx document ug363
(Virtex-6 FPGA
Memory Resources) says that dual-clock fifo should have reset signal
asserted
for at least three clock cycles.
This issue is related to issue
1063 in the wr-switch-hdl
project.
Fixed with commit cfdf688c.