wr_endpoint/ep_tx_packet_injection: initial support for hardware packet injection (testbench-proven, no HW test yet)

wr_endpoint: modified VCR1 register to allow direct access to VLAN Untagged Set/Injection Template Buffer. Also, re-generated the wishbone slaves with new wbgen2

Conflicts:
	top/spec_1_1/wr_core_demo/spec_top.ucf
	top/spec_1_1/wr_core_demo/spec_top.vhd

is at address 0. This way both CERN and GSI designs have devices located
at the same addresses on the PCI express bus.

When running "hdlmake; make" in a clean project tree, the chipscope ngc files cause the build to fail.

Conflicts:
	modules/wr_endpoint/ep_clock_alignment_fifo.vhd

Tomasz Wlostowski authored 12 years ago and Grzegorz Daniluk committed 12 years ago

Signed-off-by: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>

Tomasz Wlostowski authored 12 years ago and Grzegorz Daniluk committed 12 years ago

Signed-off-by: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>

platform/xilinx/wr_gtp_phy_spartan6: added generic for enabling/disabling GTP channels (saves logic/BUFG resources on unused channels)

tricks and constraints so that the deltaTx/Rx calibration is not necessary for every synthesized WRPC bitstream