compiled from commit:
25f814a3 update ppsi to fix 1-pps generation in Master mode

Dimitris Lampridis authored 7 years ago and Grzegorz Daniluk committed 7 years ago

PPS csync is asserted one 125MHz ref clock cycle before the actual PPS. It can be used for aligning another signal to the PPS.

Dimitris Lampridis authored 7 years ago and Grzegorz Daniluk committed 7 years ago

platform/xilinx: add generics to Xilinx platform to select which GTP channel to use (defaults to ch1)

wrpc-sw binaries compiled from commit:
a2dd8bb9: spec_defconfig: remove spaces from built-in init script

Peter Jansweijer authored 7 years ago and Grzegorz Daniluk committed 7 years ago

txts -> dio_p/n_o[2] (= Lemo 3)
rxts -> dio_p/n_o[1] (= Lemo 2; formerly used for 62.5 MHz RefClk)

Denia Bouhired-Ferrag authored 7 years ago and Maciej Lipinski committed 7 years ago

Since generic fifo has been fixed in general cores, the threshold values have been corrected accordingle and the threshold for transmission needn't have an offset to work

wrpc-sw:
24ebdb55: print also built-in init script with _init show_ cmd

Denia Bouhired-Ferrag authored 7 years ago and Maciej Lipinski committed 7 years ago

Final version of the testbench.Fully working with 6 different tests: flush, timeout, tx_thr, tx_max words, fxd latency, drop frames.

Denia Bouhired-Ferrag authored 7 years ago and Maciej Lipinski committed 7 years ago

Changed data type block so it no longer has wrd_cnt, first and last_wrd fields. Not really required anymore

Denia Bouhired-Ferrag authored 7 years ago and Maciej Lipinski committed 7 years ago

Working testbench. Runs 5 tests. Bug: does not cope with multiple block frames. only single block frames.