Commits · 3ce3214706ef1f99c8eaa6fc2d606f8ee558a0f5 · Projects / White Rabbit core collection

Aug 22, 2013
- adding submodules · 3ce32147
  Grzegorz Daniluk authored 11 years ago
  
  3ce32147
- Manifest: use proposed_master branch of general_cores · 74caf3bc
  Grzegorz Daniluk authored 11 years ago
  
  74caf3bc
Aug 14, 2013
- arria5: negative edge according to final arria5 timing model · 45e67ea3
  Wesley W. Terpstra authored 11 years ago
```
The final timing model is first available in quartus 13.0sp1
```
  45e67ea3
- eca: remove read-first memory dependency (not supported by arria5) · fbd496c1
  Wesley W. Terpstra authored 11 years ago
  
  fbd496c1
Aug 05, 2013
- wr_pps_gen: writing ESCR.SYNC=0 should disable external PPS resynchronization · f3298f17
  Tomasz Wlostowski authored 11 years ago
  
  f3298f17
- wr_pps_gen: ESCR.SEC_SET and ESCR.NSEC_SET are in reference clock domain · def59fe9
  Tomasz Wlostowski authored 11 years ago
  
  def59fe9
Jul 29, 2013
- update spec_top to match wr_core changes caused by multichannel softpll · 99bb4b6b
  Grzegorz Daniluk authored 11 years ago
  
  99bb4b6b
- top/spec: fix timing constraints for multichannel SoftPLL configuration · a34bd8df
  Tomasz Wlostowski authored 11 years ago
  
  a34bd8df
Jul 26, 2013

pps_gen: add separate flags for setting seconds and nanoseconds · fd2f6589

Grzegorz Daniluk authored 11 years ago

When WR PTP Core is set in GrandMaster mode it aligns its nanosecond
counter to 1-PPS and 10MHz coming from external source. When user wants
to set seconds counter to a desired value, the nanosecond counter was
also set (zeroed) causing additional (random) offset to the external
source.

fd2f6589

Jul 25, 2013
- Merge branch 'tom-new-softpll' · e59ec3ed
  Tomasz Wlostowski authored 11 years ago
```
Conflicts:
	modules/wr_softpll_ng/wr_softpll_ng.vhd
```
  e59ec3ed
- wr_softpll_ng: make new register layout compatible with the previous version of SoftPLL · 52a169e7
  Tomasz Wlostowski authored 11 years ago
  
  52a169e7
Jul 05, 2013
- endpoint/ep_rx_wb_master: select with generic if it should start cycle when stall is active · 0aafd085
  Grzegorz Daniluk authored 11 years ago
  
  0aafd085
Jun 12, 2013
- moved Exploder to GSI bel_projects@github · 7955995d
  Mathias Kreider authored 11 years ago
  
  7955995d
Jun 04, 2013
- xilinx/wr_gtp_phy/wr_gtp_phy_virtex6: this time really enable loopback when loopen_i is asserted · f2a6f970
  Tomasz Wlostowski authored 11 years ago and Grzegorz Daniluk committed 11 years ago
```
Signed-off-by: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
```
  f2a6f970
- wr_mini_nic/wr_mini_nic.vhd: clear TX timestamp valid flag when transmission is started · 9de79a38
  Tomasz Wlostowski authored 11 years ago and Grzegorz Daniluk committed 11 years ago
```
Signed-off-by: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
```
  9de79a38
- fabric/xwrf_mux.vhd: code cleanup · 9afbdd1e
  Tomasz Wlostowski authored 11 years ago and Grzegorz Daniluk committed 11 years ago
```
Signed-off-by: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
```
  9afbdd1e
- wr_endpoint/ep_1000basex_pcs.vhd: connect serdes loopback enable signal to PCS register block · ff5337e9
  Tomasz Wlostowski authored 11 years ago and Grzegorz Daniluk committed 11 years ago
```
Signed-off-by: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
```
  ff5337e9
May 22, 2013
- altera: update top files to use autogenerated mega functions · 055d60af
  Wesley W. Terpstra authored 11 years ago
  
  055d60af
- arria2 phy: remove generated files like the arria5 · 5f323f44
  Wesley W. Terpstra authored 11 years ago
  
  5f323f44
- altera: add support for arria5 phy · 2fd163fd
  Wesley W. Terpstra authored 11 years ago
  
  2fd163fd
May 15, 2013
- uart: moved from wr-cores to bel-projects · 2cec051e
  Stefan Rauch authored 11 years ago
```
This had nothing to do with WR, wasn't used here, and is now removed.
```
  2cec051e
May 07, 2013
- altera gxb: remove timequest work-around and remove global routing of clk_tx · 2c71597a
  Wesley W. Terpstra authored 11 years ago
  
  2c71597a
Apr 30, 2013
- altera makefiles: don't fail when a dependency is deleted · d931f4b2
  Wesley W. Terpstra authored 11 years ago
  
  d931f4b2
Apr 26, 2013
- wr_softpll_ng: 'reversed' mode for DDMTDs that does not require DDMTD counters in clk_in domain. · 0f1615da
  Tomasz Wlostowski authored 11 years ago and Grzegorz Daniluk committed 11 years ago
```
This may fix the WRs locking offsets issue & save a lot of FPGA resources.

Signed-off-by: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
```
  0f1615da
- altera: improve Makefile clean rule · 35b77aba
  Wesley W. Terpstra authored 11 years ago
  
  35b77aba
Apr 25, 2013
- eca: use revised etherbone api · f9ff1af1
  Wesley W. Terpstra authored 11 years ago
  
  f9ff1af1
Apr 24, 2013
- altera: convert programming files for raw flash programming · 51a1956b
  Wesley W. Terpstra authored 11 years ago
  
  51a1956b
Apr 23, 2013
- tlu: fix top files to work with Mathias' interface change · 9989d8b1
  Wesley W. Terpstra authored 11 years ago
  
  9989d8b1
- altera: use wishbone to program fpga's spi boot flash · 8e6ca147
  Wesley W. Terpstra authored 11 years ago
```
also, the datasheet says our new flash chips are only good to 33MHz
with slow reads. change quartus fpga load config to 20MHz (not 40).
```
  8e6ca147
Apr 19, 2013
- TLU: Merge changes to interface -> ECA timestamp format & bugfixes · aa9b79cb
  Mathias Kreider authored 11 years ago
  
  aa9b79cb
- changed interface to ECA timestamp format · e998f69e
  Mathias Kreider authored 11 years ago
```
bugfixes
```
  e998f69e
Apr 17, 2013

platform/xilinx/wr_xilinx_pkg.vhd: default values for wr_gtp_phy component inputs · 120c203d
Tomasz Wlostowski authored 11 years ago

120c203d

wr_core: adapted for multichannel SoftPLL. Added SPLL channel phase detector... · ba974a82

Tomasz Wlostowski authored 11 years ago

wr_core: adapted for multichannel SoftPLL. Added SPLL channel phase detector mode and debug FIFO enable generic parameters. Updated tm_aux_lock_en, tm_aux_locked, tm_dac_wr to support multiple aux clocks correctly

ba974a82

wr_softpll_ng: choice between Bang-Bang and DDMTD channels. Made debug FIFO... · 25811b5b

Tomasz Wlostowski authored 11 years ago

wr_softpll_ng: choice between Bang-Bang and DDMTD channels. Made debug FIFO optional in wbgen2 core (new wbgen2 required). Dynamic reconfiguration of BB dividers/gating

25811b5b

wr_softpll_ng: added choice between DDMTD or bang-bang phase detector on each output channel · fcbff05d
Tomasz Wlostowski authored 12 years ago
```
Conflicts:

	modules/wr_softpll_ng/spll_wb_slave.vhd
	modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
```
fcbff05d

modules/wr_si57x_interface: cleaned up & moved outside wr_core module · 0de330ee

Tomasz Wlostowski authored 12 years ago

Conflicts:

	Manifest.py
	modules/wr_si57x_interface/si570_if_wb.vhd
	modules/wr_si57x_interface/si570_if_wb.wb
	modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd
	modules/wr_si57x_interface/wr_si57x_interface.vhd

0de330ee

Apr 10, 2013
- exploder: work-around for older exploders without pull-down on USB reset · 9c11694d
  Wesley W. Terpstra authored 11 years ago
  
  9c11694d
- exploder: rename signals and connect final usb-wb bridge · 25d055a6
  Wesley W. Terpstra authored 11 years ago
  
  25d055a6
- altera: force quartus to place pcs->pma registers side-by-side · e80599c2
  Wesley W. Terpstra authored 11 years ago
  
  e80599c2
Apr 05, 2013
- scu: update top files · 67cc8ab3
  Wesley W. Terpstra authored 11 years ago
  
  67cc8ab3