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  1. Nov 14, 2013
  2. Nov 01, 2013
  3. Oct 28, 2013
  4. Oct 25, 2013
  5. Oct 23, 2013
  6. Oct 04, 2013
    • Wesley W. Terpstra's avatar
      altera phy: at some point tx_disparity_o timing changed => updated · ebc5758d
      Wesley W. Terpstra authored
      The WR TX path in the endpoint reset disparity to minus.
      To do this, it needs the disparity from the transceiver.
      Previously the disparity had to be delayed a few cycles.
      At some point this must have changed.
      
      Now the core goes back to sending
        0x17C = K28_5 minus
      as commas after packet boundaries.
      ebc5758d
    • Wesley W. Terpstra's avatar
      arria5 phy: use manual bitslide · 9ca2585f
      Wesley W. Terpstra authored
      The new-fangled RX clock shifting alignment in arria5 does not work.
      It is only able to shift 2 clock bits, leaving one (unreported) bit
      that gets slipped, resulting in a randomly occuring +800ps offset.
      
      Using manual bit alignment mode requires that we enable it using
      the avalon-mm management interface, however. Hence the random values
      we hard-wire into the phy_mgmt_* lines. Without writing a '1' to
      rx_enapatternalign (bit 0) in register 0x85 (pcs8g_rx_wa_control)
      you will only get a link 1/10th of the time as it does not align.
      9ca2585f
  7. Sep 27, 2013
  8. Sep 26, 2013
  9. Sep 23, 2013
  10. Sep 17, 2013
    • Wesley W. Terpstra's avatar
      arria5: expose async transceiver lock signal · 2af1fd96
      Wesley W. Terpstra authored
      Now that we reset all PLLs together, the transceiver lock must
      not depend on clk_sys running.
      2af1fd96
    • Wesley W. Terpstra's avatar
      arria5: work around buggy PLL reset and compensate phase · e6062d61
      Wesley W. Terpstra authored
      The problems with white rabbit reliability on arria5 were due to
      two problems, both due to the WR reference fPLL.
      
      Problem #1:
      
      The fPLLs do not lock properly at power-on. They often ended up with
      outputs that are aligned to the VCO but not the input clock. This
      caused problems because it destroys the ref-tx phase relationship.
      
      This is solved by including a core to reset the PLLs.
      
      Problem #2:
      
      Both the fPLL and transceiver introduce delay relative to the WR input
      clock. Unfortunately, timequest does NOT analysis this phase relationship.
      In order to ensure a safe transfer between the domains, we must:
      a) logic lock the clk_tx and clk_ref registers beside each other
      b) find the right fPLL offset to feed the clk_tx
      
      I tried every nanosecond phase offset and recorded the results of WR below:
         0 xoxoooooxxxxxx
      1000 ................
      2000 ................
      3000 ...............
      4000 ............
      5000 .x.xx.xx.x..xxx
      6000 xxxxxxxxxxxxxxx
      7000 xxxxxxxxxxxxxx
      
      . = successful track
      x = sync phase hangs at -4000ps
      o = track phase that goes crazy
      e6062d61
  11. Sep 16, 2013
  12. Sep 10, 2013
    • Wesley W. Terpstra's avatar
      arria5: adjust PLL phases · 109df05b
      Wesley W. Terpstra authored
      When outputting multiple clocks from the same PLL, the arria5 does
      not appear to maintain their phase relationships in direct mode.
      Thus, switch them all to source synchronous to hold the relationship.
      
      Furthermore, the fpga/spi-flash timing requires a -1.5ns offset.
      I measure that it works with +9ns, +8ns and fails with +10ns and +7ns.
      Thus, I set the flash phase to +8.5ns = -1.5ns.
      109df05b
  13. Sep 03, 2013
  14. Aug 28, 2013
  15. Aug 27, 2013
  16. Aug 26, 2013
  17. Aug 22, 2013
  18. Aug 14, 2013
  19. Aug 05, 2013