Peter Jansweijer authored 10 years ago and Grzegorz Daniluk committed 9 years ago

added tx_prbs_sel, sfp_tx_disable, sfp_loss, sfp_tx_fault and full width loopback to MDIO Control register. Be careful: Single bit loopback was relocated to accomodate loopback(2:0)!

Otherwise, hdlmake complains.

modules/endpoint: count rx frames at the end of rx_path chain and let wr_endpoint decide which one to export

It was usefull when debugging the SWcore on high traffic load.

When rx buffer is full when new SOF arrives, the whole frame is dropped and not
stored in the buffer. However, RTU request was still generated by the
ep_rtu_header_extract.
This patch prevents ep_rtu_header_extract from generating rtu request, when
rxbuf is full on SOF.

phy_rdy_i was needed to fix the Virtex-6 FIFO reseting issue on the WRS.
However, WRPC uses inferred fifo which has fully asynchronous reset and does not
suffer from this bug. Therefore in case of the WRPC this signal can be tied to
'1' or drived from the GTP serdes.

Earlier we were resetting clock alignment fifo (ep_rx_path) when GTX was still
not locked and was not producing rx clock. Xilinx document ug363 (Virtex-6 FPGA
Memory Resources) says that dual-clock fifo should have reset signal asserted
for at least three clock cycles. Chipscope says our fifo was reset while rx
clock was not yet there. This apparently was causing Xilinx fifo block going
crazy once every few boots. As a result FIFO was asserting _empty_ and
_almost_full_ outputs at the same time causing the rx path to stall forever.

platform/xilinx: adding rdy_o to gtx and gtp wrappers to indicate when serdes is ready and produces rx clock

If one of them is full, the othe one has to drop a frame as well. Otherwise they
are not in sync any more and we have more pfilter decisions than frames or the
other way round.

endpoint/rx_vlan_unit: trivial clean-up, removing _old-stuff_ comments, we use git, no need to keep them

endpoint/rx_vlan_unit: when we're storing first fab word in the INSERT_TAG state, it's not necessarily always valid

Previous implementation caused dvalid=1 in Idle state too early in some cases
(large traffic) so that the non-valid data word is validated.

If we don't pad 802.1q frames 4-bytes more than regular frames, they become runt
frames after untagging (when port is in ACCESS mode).

If there is a storm of frames and rx_buffer gets full it starts to drop frames.
However, before this commit even if a frame was dropped that way, U_match_buffer
was storing pfilter decision for that frame. As a result decisions coming out
from the match_buffer were shifted and applied to wrong frames. With this commit
I check if the rx_buffer is full at the beginning of frame and eventually block
mbuf_we so that the pfilter decision is not stored.

Otherwise we miss tx timestamp if there is a lot of other traffic.

Cesar Prados authored 10 years ago and Grzegorz Daniluk committed 10 years ago

    If an external module sends packets from the WR fabric and requests
    a Tx Ts, the TS were not going to the external IF but to the minic
    as this packets were sent from the LM32, as a result, the wrpc-sw/ppsi
    was getting confuse with the PTP TS and ext TS and losing the node
    synchronization. That was because the TS strobe line was only connected to
    the minic for every source of TS. This commit mux the stb line depending on
    the frame_id. For packets sent from LM32 (wrpc-sw) the id is 0x0, packets sent
    from an external module should use whatever id, but never 0x0.

testbench/wrc_core: improved testbench to send/receive/verify reception frames of every possible size (incl. padded runt frames)

Otherwise, when only part of a frame is received (due to error),
decoding oob fails anyway.

Peter Jansweijer authored 11 years ago and Grzegorz Daniluk committed 10 years ago

If, for some reason, a proper alignment is missed then the cur_slide counter
might increment outside its window (0..9 for an 8 bit Phy and 0..19 for a 16 bit
Phy). Apparently nobody ever missed an alignment, but it might fail someday,
somehow, sometime... Therefore it is wise to put the module function in place.
The module function was implemented using an if statement because synthesis
tools complained about the VHDL "mod" function.

Conflicts:

	modules/wrc_core/wr_core.vhd
	top/spec_1_1/wr_core_demo/spec_top.vhd

Based on Peter's work, ported to current wr_endpoint code.

wr_endpoint/ep_rx_path: don't instantiate U_match_buffer when neither early match nor pfilter are there

Otherwise, FSM cannot react on time under a storm of traffic.

When it was doing that, for short frames pclass and drop_o were zeroed
and U_match_buffer was not getting correct values.

Although fab_dreq is low in FINISH_CYCLE state, ep_rx_buffer outputs SOF in the
same cycle it gets fab_dreq low. That means we may get SOF while still in
FINISH_CYCLE state, and we lose it if not stored in a register.

Peter Jansweijer authored 11 years ago and Grzegorz Daniluk committed 10 years ago

Precision synthesis complains "Error: Net is driven by multiple primitive gates
-- NET: regs_towb_dmcr_n_avg_i(11:0)"
This is due to the fact that when g_with_dmtd is true then
"regs_towb.dmcr_n_avg_i" was driven. This signal should be orred as the rest of
regs_towb assignment.