it contains streamers as well as a WB-accessible registers for:
- reading/controling statistics (module to be added)
- debugging
- controlling streamers, e.g. reset sequence

created the folder struture as discussed with Maciej && added wr-core spec_top.vhd as a starting point && added needed git submodules && added Olb B hdl code

Maciej Lipinski authored 9 years ago and Tomasz Wlostowski committed 9 years ago

The added code is based on the one provided for White Rabbit Core Hands-on
Training (http://www.ohwr.org/projects/wr-cores/wiki/Handson_training). The
code has been only adapted to
- fit the structure of wr-cores repository
- work with the newest wrpc-v3.0

Conflicts:

	Manifest.py
	modules/wr_si57x_interface/si570_if_wb.vhd
	modules/wr_si57x_interface/si570_if_wb.wb
	modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd
	modules/wr_si57x_interface/wr_si57x_interface.vhd

Stefan Rauch authored 12 years ago and Wesley W. Terpstra committed 12 years ago

  * Added the new SCU2 target (different pinouts and components)
  * Moved common components (uart) to modules
  * Moved the common spec and SCU DAC files into modules
  * Added the DDR3 controller for Altera
  * Removed a few superfluous files from version control