Stefan Rauch authored 12 years ago and Wesley W. Terpstra committed 12 years ago

  * Added the new SCU2 target (different pinouts and components)
  * Moved common components (uart) to modules
  * Moved the common spec and SCU DAC files into modules
  * Added the DDR3 controller for Altera
  * Removed a few superfluous files from version control

The problem was that the WR core did not expose the err and rty lines.
If a device ever used these lines (the crossbar does for example),
then the master would get hung waiting for an answer.

Stefan Rauch authored 12 years ago and Wesley W. Terpstra committed 12 years ago

changed WR SFP to SFP2

wr_core: wired clk_aux clock (1 channel), default values for inputs, added tm_link_up_o output and wired aux DAC signals