- Sep 27, 2013
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Wesley W. Terpstra authored
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- Sep 26, 2013
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
These paths are not covered by the SDC clock files, because they can interact between outputs of the same PLL.
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Wesley W. Terpstra authored
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Mathias Kreider authored
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Wesley W. Terpstra authored
Allow any order (to/downto) of the natural_vector generic inputs. Document and prove correctness of the phase trap.
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Wesley W. Terpstra authored
phase: start-up assuming we need to shift => no glitchy resets
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Wesley W. Terpstra authored
It will be useful in the future to control phases of all output clocks. Split out and improve this functionality, and then gut the butis aligner. There is also now no need to hard-ware phase offsets in the ref PLL.
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- Sep 23, 2013
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Wesley W. Terpstra authored
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- Sep 17, 2013
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Wesley W. Terpstra authored
Now that we reset all PLLs together, the transceiver lock must not depend on clk_sys running.
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Wesley W. Terpstra authored
The problems with white rabbit reliability on arria5 were due to two problems, both due to the WR reference fPLL. Problem #1: The fPLLs do not lock properly at power-on. They often ended up with outputs that are aligned to the VCO but not the input clock. This caused problems because it destroys the ref-tx phase relationship. This is solved by including a core to reset the PLLs. Problem #2: Both the fPLL and transceiver introduce delay relative to the WR input clock. Unfortunately, timequest does NOT analysis this phase relationship. In order to ensure a safe transfer between the domains, we must: a) logic lock the clk_tx and clk_ref registers beside each other b) find the right fPLL offset to feed the clk_tx I tried every nanosecond phase offset and recorded the results of WR below: 0 xoxoooooxxxxxx 1000 ................ 2000 ................ 3000 ............... 4000 ............ 5000 .x.xx.xx.x..xxx 6000 xxxxxxxxxxxxxxx 7000 xxxxxxxxxxxxxx . = successful track x = sync phase hangs at -4000ps o = track phase that goes crazy
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- Sep 16, 2013
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Wesley W. Terpstra authored
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- Sep 10, 2013
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Wesley W. Terpstra authored
When outputting multiple clocks from the same PLL, the arria5 does not appear to maintain their phase relationships in direct mode. Thus, switch them all to source synchronous to hold the relationship. Furthermore, the fpga/spi-flash timing requires a -1.5ns offset. I measure that it works with +9ns, +8ns and fails with +10ns and +7ns. Thus, I set the flash phase to +8.5ns = -1.5ns.
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- Sep 03, 2013
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Mathias Kreider authored
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- Aug 28, 2013
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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- Aug 27, 2013
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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- Aug 26, 2013
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Wesley W. Terpstra authored
In the FAIR project, we need to reproduce the BuTiS clock. It runs at 200MHz and should be aligned to the PPS. This commit adds a 200MHz clock output from the WR ref PLL. A small core uses Altera's phase compensation feature to align the 200MHz rising edge with the PPS, by leveraging a third 25MHz output signal which can be used to detect the 125-200 relationship.
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- Aug 22, 2013
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Wesley W. Terpstra authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- Aug 14, 2013
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Wesley W. Terpstra authored
The final timing model is first available in quartus 13.0sp1
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Wesley W. Terpstra authored
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- Aug 05, 2013
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- Jul 29, 2013
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Grzegorz Daniluk authored
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Tomasz Wlostowski authored
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- Jul 26, 2013
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Grzegorz Daniluk authored
When WR PTP Core is set in GrandMaster mode it aligns its nanosecond counter to 1-PPS and 10MHz coming from external source. When user wants to set seconds counter to a desired value, the nanosecond counter was also set (zeroed) causing additional (random) offset to the external source.
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- Jul 25, 2013
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Tomasz Wlostowski authored
Conflicts: modules/wr_softpll_ng/wr_softpll_ng.vhd
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Tomasz Wlostowski authored
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- Jul 05, 2013
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Grzegorz Daniluk authored
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- Jun 12, 2013
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Mathias Kreider authored
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- Jun 04, 2013
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Signed-off-by:
Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
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Signed-off-by:
Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
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Signed-off-by:
Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
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