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  1. Sep 27, 2013
  2. Sep 26, 2013
  3. Sep 23, 2013
  4. Sep 17, 2013
    • Wesley W. Terpstra's avatar
      arria5: expose async transceiver lock signal · 2af1fd96
      Wesley W. Terpstra authored
      Now that we reset all PLLs together, the transceiver lock must
      not depend on clk_sys running.
      2af1fd96
    • Wesley W. Terpstra's avatar
      arria5: work around buggy PLL reset and compensate phase · e6062d61
      Wesley W. Terpstra authored
      The problems with white rabbit reliability on arria5 were due to
      two problems, both due to the WR reference fPLL.
      
      Problem #1:
      
      The fPLLs do not lock properly at power-on. They often ended up with
      outputs that are aligned to the VCO but not the input clock. This
      caused problems because it destroys the ref-tx phase relationship.
      
      This is solved by including a core to reset the PLLs.
      
      Problem #2:
      
      Both the fPLL and transceiver introduce delay relative to the WR input
      clock. Unfortunately, timequest does NOT analysis this phase relationship.
      In order to ensure a safe transfer between the domains, we must:
      a) logic lock the clk_tx and clk_ref registers beside each other
      b) find the right fPLL offset to feed the clk_tx
      
      I tried every nanosecond phase offset and recorded the results of WR below:
         0 xoxoooooxxxxxx
      1000 ................
      2000 ................
      3000 ...............
      4000 ............
      5000 .x.xx.xx.x..xxx
      6000 xxxxxxxxxxxxxxx
      7000 xxxxxxxxxxxxxx
      
      . = successful track
      x = sync phase hangs at -4000ps
      o = track phase that goes crazy
      e6062d61
  5. Sep 16, 2013
  6. Sep 10, 2013
    • Wesley W. Terpstra's avatar
      arria5: adjust PLL phases · 109df05b
      Wesley W. Terpstra authored
      When outputting multiple clocks from the same PLL, the arria5 does
      not appear to maintain their phase relationships in direct mode.
      Thus, switch them all to source synchronous to hold the relationship.
      
      Furthermore, the fpga/spi-flash timing requires a -1.5ns offset.
      I measure that it works with +9ns, +8ns and fails with +10ns and +7ns.
      Thus, I set the flash phase to +8.5ns = -1.5ns.
      109df05b
  7. Sep 03, 2013
  8. Aug 28, 2013
  9. Aug 27, 2013
  10. Aug 26, 2013
  11. Aug 22, 2013
  12. Aug 14, 2013
  13. Aug 05, 2013
  14. Jul 29, 2013
  15. Jul 26, 2013
    • Grzegorz Daniluk's avatar
      pps_gen: add separate flags for setting seconds and nanoseconds · fd2f6589
      Grzegorz Daniluk authored
      When WR PTP Core is set in GrandMaster mode it aligns its nanosecond
      counter to 1-PPS and 10MHz coming from external source. When user wants
      to set seconds counter to a desired value, the nanosecond counter was
      also set (zeroed) causing additional (random) offset to the external
      source.
      fd2f6589
  16. Jul 25, 2013
  17. Jul 05, 2013
  18. Jun 12, 2013
  19. Jun 04, 2013