In wrpc-v5, LM32 is replaced by RISC-V. Hence, the new compiled WRPC software
for the simulation is added (wrc.bram file).
Also, the size of the RAM used by the WRPC software is increased.
The testbench sets hdl_testbench structure used for communication with the software.
The simulation works with ModelSim.

Peter Jansweijer authored 5 years ago and Grzegorz Daniluk committed 5 years ago

add wrpc/wrc_phy16_direct_dmtd.bram (spll KP parameters times 5 due to VCXOs range 20 ppm, incremented mode master lock timeout)
wrc_phy16_direct_dmtd.bram build with:
wrpc-sw.git peter_direct_dmtd SHA 50f1c0e
ppsi.git peter_direct_dmtd SHA bf5f6de

this is needed for WR-BTrain-VXS release

[VXS support/bin] updated WRPC binary with fixes and support for FRAM in VXS (tmp solution, clean version to be added to WRPC SW)

- fixed one-wire reading of thermometer ID to create MAC
- added reading of FRAM (temporarily instead of FLASH)

compiled from commit:
a9add108 Merge branch 'adam-lldp-rebased' into proposed_master

Compiled from wrpc-sw commit:
c0e116b: simpler sdbfs creation by using parameters provided by Syscon HDL module

Maciej Lipinski authored 7 years ago and Grzegorz Daniluk committed 7 years ago

The binary did not work. I do not know why. I just recompiled wrpc-sw
with wrpc_sim_defconfig configuration and it works.

compiled from commit:
25f814a update ppsi to fix 1-pps generation in Master mode

wrpc-sw binaries compiled from commit:
a2dd8bb9: spec_defconfig: remove spaces from built-in init script

wrpc-sw:
24ebdb5: print also built-in init script with _init show_ cmd

Dimitris Lampridis authored 7 years ago and Grzegorz Daniluk committed 7 years ago

bin: modfied wrpc-sw for simulations to not perform SDB discovery, in order to speed-up simulation time

built from wrpc-sw using commit:
91ab423 sim main: disable discovery of peripherals via SDB to speed-up the simulation.

Compiled from commit 180419ee of wrpc-sw repo.