.gitignore

modules/wr_tbi_phy/Manifest.py

modules/wrc_core/wrc_periph.vhd

platform/altera/Manifest.py

platform/altera/wr_altera_pkg.vhd

platform/altera/wr_arria10_phy/.gitignore

platform/altera/wr_arria10_phy/Manifest.py

..._atx_pll/.qsys_edit/wr_arria10_e3p1_atx_pll_schematic.nlv

.../wr_arria10_e3p1_atx_pll/wr_arria10_e3p1_atx_pll.BAK.qsys

..._phy/wr_arria10_e3p1_atx_pll/wr_arria10_e3p1_atx_pll.qsys

...3p1_atx_pll/altera_xcvr_atx_pll_a10_181/sim/a10_avmm_h.sv

...x_pll/altera_xcvr_atx_pll_a10_181/sim/a10_xcvr_atx_pll.sv

...1_atx_pll/altera_xcvr_atx_pll_a10_181/sim/aldec_files.txt

...x_pll/altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_arbiter.sv

...era_xcvr_atx_pll_a10_181/sim/alt_xcvr_atx_pll_rcfg_arb.sv

...ll_a10_181/sim/alt_xcvr_atx_pll_rcfg_opt_logic_chk6tua.sv

...ll_a10_181/sim/alt_xcvr_atx_pll_rcfg_opt_logic_lhyn27i.sv

...ll_a10_181/sim/alt_xcvr_atx_pll_rcfg_opt_logic_z7ksuua.sv

.../altera_xcvr_atx_pll_a10_181/sim/alt_xcvr_pll_avmm_csr.sv

...a_xcvr_atx_pll_a10_181/sim/alt_xcvr_pll_embedded_debug.sv