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Commit ac7c1f86 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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endpoint WB: temporarily enabled legacy (HW) phase tracker

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modules/wr_endpoint/ep_registers_pkg.vhd
+ 17
− 3
View file @ ac7c1f86
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_registers_pkg.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created : Wed Oct 26 22:05:09 2011
-- Created : Sun Oct 30 00:20:59 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
......@@ -30,6 +30,8 @@ package ep_wbgen2_pkg is
mdio_asr_ready_i : std_logic;
dsr_lstatus_i : std_logic;
dsr_lact_i : std_logic;
dmsr_ps_val_i : std_logic_vector(23 downto 0);
dmsr_ps_rdy_i : std_logic;
end record;
constant c_ep_in_registers_init_value: t_ep_in_registers := (
......@@ -41,7 +43,9 @@ package ep_wbgen2_pkg is
mdio_asr_rdata_i => (others => '0'),
mdio_asr_ready_i => '0',
dsr_lstatus_i => '0',
dsr_lact_i => '0'
dsr_lact_i => '0',
dmsr_ps_val_i => (others => '0'),
dmsr_ps_rdy_i => '0'
);
-- Output registers (WB slave -> user design)
......@@ -90,6 +94,10 @@ package ep_wbgen2_pkg is
mdio_asr_phyad_o : std_logic_vector(7 downto 0);
dsr_lact_o : std_logic;
dsr_lact_load_o : std_logic;
dmcr_en_o : std_logic;
dmcr_n_avg_o : std_logic_vector(11 downto 0);
dmsr_ps_rdy_o : std_logic;
dmsr_ps_rdy_load_o : std_logic;
end record;
constant c_ep_out_registers_init_value: t_ep_out_registers := (
......@@ -135,7 +143,11 @@ package ep_wbgen2_pkg is
mdio_cr_rw_o => '0',
mdio_asr_phyad_o => (others => '0'),
dsr_lact_o => '0',
dsr_lact_load_o => '0'
dsr_lact_load_o => '0',
dmcr_en_o => '0',
dmcr_n_avg_o => (others => '0'),
dmsr_ps_rdy_o => '0',
dmsr_ps_rdy_load_o => '0'
);
function "or" (left, right: t_ep_in_registers) return t_ep_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
......@@ -162,6 +174,8 @@ tmp.mdio_asr_rdata_i := left.mdio_asr_rdata_i or right.mdio_asr_rdata_i;
tmp.mdio_asr_ready_i := left.mdio_asr_ready_i or right.mdio_asr_ready_i;
tmp.dsr_lstatus_i := left.dsr_lstatus_i or right.dsr_lstatus_i;
tmp.dsr_lact_i := left.dsr_lact_i or right.dsr_lact_i;
tmp.dmsr_ps_val_i := left.dmsr_ps_val_i or right.dmsr_ps_val_i;
tmp.dmsr_ps_rdy_i := left.dmsr_ps_rdy_i or right.dmsr_ps_rdy_i;
return tmp;
end function;
end package body;
modules/wr_endpoint/ep_wishbone_controller.vhd
+ 78
− 17
View file @ ac7c1f86
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_wishbone_controller.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created : Wed Oct 26 22:05:09 2011
-- Created : Sun Oct 30 00:20:59 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
......@@ -84,6 +84,8 @@ signal ep_macl_int : std_logic_vector(31 downto 0);
signal ep_mdio_cr_addr_int : std_logic_vector(7 downto 0);
signal ep_mdio_cr_rw_int : std_logic ;
signal ep_mdio_asr_phyad_int : std_logic_vector(7 downto 0);
signal ep_dmcr_en_int : std_logic ;
signal ep_dmcr_n_avg_int : std_logic_vector(11 downto 0);
signal ep_rmon_ram_rddata_int : std_logic_vector(31 downto 0);
signal ep_rmon_ram_rd_int : std_logic ;
signal ep_rmon_ram_wr_int : std_logic ;
......@@ -153,6 +155,9 @@ begin
ep_mdio_cr_rw_int <= '0';
ep_mdio_asr_phyad_int <= "00000000";
regs_o.dsr_lact_load_o <= '0';
ep_dmcr_en_int <= '0';
ep_dmcr_n_avg_int <= "000000000000";
regs_o.dmsr_ps_rdy_load_o <= '0';
elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -167,6 +172,7 @@ begin
regs_o.pfcr0_mm_data_msb_wr_o <= '0';
regs_o.mdio_cr_data_wr_o <= '0';
regs_o.dsr_lact_load_o <= '0';
regs_o.dmsr_ps_rdy_load_o <= '0';
ack_in_progress <= '0';
else
ep_tscr_cs_start_int <= ep_tscr_cs_start_int_delay;
......@@ -178,13 +184,14 @@ begin
regs_o.pfcr0_mm_data_msb_wr_o <= '0';
regs_o.mdio_cr_data_wr_o <= '0';
regs_o.dsr_lact_load_o <= '0';
regs_o.dmsr_ps_rdy_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(5) is
when '0' =>
case rwaddr_reg(3 downto 0) is
when "0000" =>
case rwaddr_reg(4 downto 0) is
when "00000" =>
if (wb_we_i = '1') then
ep_ecr_portid_int <= wrdata_reg(4 downto 0);
ep_ecr_rst_cnt_int <= wrdata_reg(5);
......@@ -229,7 +236,7 @@ begin
end if;
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "0001" =>
when "00001" =>
if (wb_we_i = '1') then
rddata_reg(0) <= 'X';
ep_tscr_en_txts_int <= wrdata_reg(0);
......@@ -275,7 +282,7 @@ begin
end if;
ack_sreg(4) <= '1';
ack_in_progress <= '1';
when "0010" =>
when "00010" =>
if (wb_we_i = '1') then
rddata_reg(0) <= 'X';
ep_rfcr_a_runt_int <= wrdata_reg(0);
......@@ -303,7 +310,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011" =>
when "00011" =>
if (wb_we_i = '1') then
ep_vcr0_qmode_int <= wrdata_reg(1 downto 0);
rddata_reg(2) <= 'X';
......@@ -332,7 +339,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100" =>
when "00100" =>
if (wb_we_i = '1') then
regs_o.vcr1_vid_wr_o <= '1';
regs_o.vcr1_value_wr_o <= '1';
......@@ -372,7 +379,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101" =>
when "00101" =>
if (wb_we_i = '1') then
regs_o.pfcr0_mm_addr_wr_o <= '1';
regs_o.pfcr0_mm_write_wr_o <= '1';
......@@ -415,7 +422,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110" =>
when "00110" =>
if (wb_we_i = '1') then
ep_pfcr1_mm_data_lsb_int <= wrdata_reg(11 downto 0);
else
......@@ -443,7 +450,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111" =>
when "00111" =>
if (wb_we_i = '1') then
ep_tcar_pcp_map_int <= wrdata_reg(23 downto 0);
else
......@@ -459,7 +466,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" =>
when "01000" =>
if (wb_we_i = '1') then
rddata_reg(0) <= 'X';
ep_fcr_rxpause_int <= wrdata_reg(0);
......@@ -481,7 +488,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001" =>
when "01001" =>
if (wb_we_i = '1') then
ep_mach_int <= wrdata_reg(15 downto 0);
else
......@@ -505,7 +512,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1010" =>
when "01010" =>
if (wb_we_i = '1') then
ep_macl_int <= wrdata_reg(31 downto 0);
else
......@@ -513,7 +520,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1011" =>
when "01011" =>
if (wb_we_i = '1') then
regs_o.mdio_cr_data_wr_o <= '1';
ep_mdio_cr_addr_int <= wrdata_reg(23 downto 16);
......@@ -548,7 +555,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1100" =>
when "01100" =>
if (wb_we_i = '1') then
ep_mdio_asr_phyad_int <= wrdata_reg(23 downto 16);
rddata_reg(31) <= 'X';
......@@ -566,14 +573,14 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1101" =>
when "01101" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= "11001010111111101011101010111110";
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1110" =>
when "01110" =>
if (wb_we_i = '1') then
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
......@@ -614,6 +621,53 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111" =>
if (wb_we_i = '1') then
rddata_reg(0) <= 'X';
ep_dmcr_en_int <= wrdata_reg(0);
ep_dmcr_n_avg_int <= wrdata_reg(27 downto 16);
else
rddata_reg(0) <= ep_dmcr_en_int;
rddata_reg(27 downto 16) <= ep_dmcr_n_avg_int;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000" =>
if (wb_we_i = '1') then
rddata_reg(24) <= 'X';
regs_o.dmsr_ps_rdy_load_o <= '1';
else
rddata_reg(23 downto 0) <= regs_i.dmsr_ps_val_i;
rddata_reg(24) <= regs_i.dmsr_ps_rdy_i;
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
......@@ -787,6 +841,13 @@ begin
-- Link status
-- Link activity
regs_o.dsr_lact_o <= wrdata_reg(1);
-- DMTD Phase measurement enable
regs_o.dmcr_en_o <= ep_dmcr_en_int;
-- DMTD averaging samples
regs_o.dmcr_n_avg_o <= ep_dmcr_n_avg_int;
-- DMTD Phase shift value
-- DMTD Phase shift value ready
regs_o.dmsr_ps_rdy_o <= wrdata_reg(24);
-- extra code for reg/fifo/mem: Event counters memory
-- RAM block instantiation for memory: Event counters memory
ep_rmon_ram_raminst : wbgen2_dpssram
......
modules/wr_endpoint/ep_wishbone_controller.wb
+ 49
− 0
View file @ ac7c1f86
......@@ -585,6 +585,55 @@ peripheral {
};
};
reg {
name = "DMTD Control Register";
prefix = "DMCR";
field {
name = "DMTD Phase measurement enable";
description = "1: enables DMTD phase measurement";
type = BIT;
prefix = "EN";
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "DMTD averaging samples";
description = "Number of raw DMTD phase samples averaged in every measurement cycle";
prefix = "N_AVG";
type = SLV;
size = 12;
align = 16;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
};
reg {
name = "DMTD Status register";
prefix = "DMSR";
field {
name = "DMTD Phase shift value";
prefix = "PS_VAL";
size = 24;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "DMTD Phase shift value ready";
prefix = "PS_RDY";
type = BIT;
load = LOAD_EXT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
};
};
ram {
name = "Event counters memory";
description = "RMON event counters:\
......
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