Merge branch 'wishbonized' of ohwr.org:hdl-core-lib/wr-cores into wishbonized

Conflicts:
	top/spec_1_1/wr_core_demo/spec_top.vhd

Manifest.py

@@ -12,6 +12,3 @@ modules =  {"local" :
 												"modules/wrc_core" ],
 						"git" : "git://ohwr.org/hdl-core-lib/general-cores.git::wishbone_with_adapter"
 						}
-												
-										
-												
\ No newline at end of file

modules/wrc_core/wr_core.vhd

@@ -6,7 +6,7 @@
 -- Author     : Grzegorz Daniluk
 -- Company    : Elproma
 -- Created    : 2011-02-02
--- Last update: 2011-11-09
+-- Last update: 2011-12-09
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
 -------------------------------------------------------------------------------