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Commit a1f138cf authored by Imre Pechan's avatar Imre Pechan
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fix interfaces and xdc

parent 7ef1e052
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......@@ -47,7 +47,7 @@ package wr_damc_fmc2zup_pkg is
-- set to 1 to speed up some initialization processes during simulation
g_simulation : integer := 0;
-- Select whether to include external ref clock input
g_with_external_clock_input : boolean := TRUE;
g_with_external_clock_input : boolean := FALSE;
-- Number of aux clocks syntonized by WRPC to WR timebase
g_aux_clks : integer := 0;
-- plain = expose WRC fabric interface
......@@ -82,7 +82,6 @@ package wr_damc_fmc2zup_pkg is
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp_n_i : in std_logic;
clk_125m_gtp_p_i : in std_logic;
clk_125m_pci_i : in std_logic;
-- Aux clocks, which can be disciplined by the WR Core
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
-- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
......@@ -221,7 +220,7 @@ package wr_damc_fmc2zup_pkg is
---------------------------------------------------------------------------
-- Aux clocks control
---------------------------------------------------------------------------
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_value_o : out std_logic_vector(31 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
......
......@@ -45,7 +45,7 @@ entity xwrc_board_damc_fmc2zup is
-- set to 1 to speed up some initialization processes during simulation
g_simulation : integer := 0;
-- Select whether to include external ref clock input
g_with_external_clock_input : boolean := TRUE;
g_with_external_clock_input : boolean := FALSE;
-- Number of aux clocks syntonized by WRPC to WR timebase
g_aux_clks : integer := 0;
-- plain = expose WRC fabric interface
......@@ -80,7 +80,6 @@ entity xwrc_board_damc_fmc2zup is
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp_n_i : in std_logic;
clk_125m_gtp_p_i : in std_logic;
clk_125m_pci_i : in std_logic;
-- Aux clocks, which can be disciplined by the WR Core
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
-- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
......@@ -219,7 +218,7 @@ entity xwrc_board_damc_fmc2zup is
---------------------------------------------------------------------------
-- Aux clocks control
---------------------------------------------------------------------------
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_value_o : out std_logic_vector(31 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
......@@ -316,10 +315,6 @@ architecture struct of xwrc_board_damc_fmc2zup is
signal wb_slave_in : t_wishbone_slave_in;
signal zero : std_logic;
-- GTH clock path
signal clk_125m_gth_bufds : std_logic;
signal clk_125m_gth : std_logic;
-- EEPROM IIC signals
signal eeprom_sda_i : std_logic;
signal eeprom_sda_o : std_logic;
......@@ -338,35 +333,6 @@ architecture struct of xwrc_board_damc_fmc2zup is
begin -- architecture struct
-----------------------------------------------------------------------------
-- Clock buffers for GTH clock
-----------------------------------------------------------------------------
cmp_ibufds_gte4 : IBUFDS_GTE4
generic map (
REFCLK_EN_TX_PATH => '0', -- Refer to Transceiver User Guide
REFCLK_HROW_CK_SEL => "00", -- Refer to Transceiver User Guide
REFCLK_ICNTL_RX => "00" -- Refer to Transceiver User Guide
)
port map (
O => open, -- 1-bit output: Refer to Transceiver User Guide
ODIV2 => clk_125m_gth_bufds, -- 1-bit output: Refer to Transceiver User Guide
CEB => '0', -- 1-bit input: Refer to Transceiver User Guide
I => clk_125m_gtp_p_i, -- 1-bit input: Refer to Transceiver User Guide
IB => clk_125m_gtp_n_i -- 1-bit input: Refer to Transceiver User Guide
);
cmp_bufg_gt : BUFG_GT
port map (
O => clk_125m_gth, -- 1-bit output: Buffer
CE => '1', -- 1-bit input: Buffer enable
CEMASK => '0', -- 1-bit input: CE Mask
CLR => '0', -- 1-bit input: Asynchronous clear
CLRMASK => '0', -- 1-bit input: CLR Mask
DIV => "000", -- 3-bit input: Dynamic divide Value
I => clk_125m_gth_bufds -- 1-bit input: Buffer
);
-----------------------------------------------------------------------------
-- I2C signals
-----------------------------------------------------------------------------
......@@ -397,7 +363,7 @@ begin -- architecture struct
cmp_xwrc_platform : xwrc_platform_xilinx
generic map (
g_fpga_family => "zynqultrascaleplus",
g_fpga_family => "zynqus",
g_with_external_clock_input => g_with_external_clock_input,
g_use_default_plls => TRUE,
g_simulation => g_simulation)
......@@ -406,9 +372,8 @@ begin -- architecture struct
clk_10m_ext_i => clk_10m_ext_i,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_i => clk_125m_pllref_buf,
clk_125m_gtp_p_i => '0',
clk_125m_gtp_n_i => '0',
clk_125m_pci_i => clk_125m_gth,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
sfp_txn_o => sfp_txn_o,
sfp_txp_o => sfp_txp_o,
sfp_rxn_i => sfp_rxn_i,
......
set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets clk_200]
#set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets clk_200]
create_clock -name clk_20m_vcxo -period 50 [get_ports clk_20m_vcxo_i]
create_clock -name clk_125m_pllref -period 8 [get_ports clk_125m_pllref_p_i]
......@@ -8,10 +8,15 @@ create_clock -name clk_200 -period 5 [get_ports clk_200_p]
# rename auto-generated clock to give specific name
# (see output of report_clock command for details)
create_generated_clock -name wr_pll0_clk0 [get_pins {cmp_xwrc_board_damc_fmc2zup/cmp_xwrc_platform/gen_default_plls.gen_zynqultrascaleplus_default_plls.cmp_sys_clk_pll/CLKOUT0}]
#create_generated_clock -name wr_pll0_clk0 [get_pins {cmp_xwrc_board_damc_fmc2zup/cmp_xwrc_platform/gen_default_plls.gen_zynqultrascaleplus_default_plls.cmp_sys_clk_pll/CLKOUT0}]
set_false_path -to [get_pins {cmp_xwrc_board_damc_fmc2zup/cmp_board_common/cmp_xwr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/gen_straight.clk_i_d0_reg/D}]
set_false_path -to [get_pins {cmp_xwrc_board_damc_fmc2zup/cmp_board_common/cmp_xwr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/gen_straight.clk_i_d0_reg/D}]
set_false_path -to [get_pins {cmp_xwrc_board_damc_fmc2zup/cmp_board_common/cmp_xwr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/U_sync_tag_strobe/sync_posedge.sync0_reg/D}]
#set_false_path -to [get_pins {cmp_xwrc_board_damc_fmc2zup/cmp_board_common/cmp_xwr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/gen_straight.clk_i_d0_reg/D}]
#set_false_path -to [get_pins {cmp_xwrc_board_damc_fmc2zup/cmp_board_common/cmp_xwr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/gen_straight.clk_i_d0_reg/D}]
#set_false_path -to [get_pins {cmp_xwrc_board_damc_fmc2zup/cmp_board_common/cmp_xwr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/U_sync_tag_strobe/sync_posedge.sync0_reg/D}]
set_clock_groups -asynchronous -group [get_clocks clk_pl_1] -group [get_clocks wr_pll0_clk0] -group [get_clocks clk_125m_pllref]
# set_clock_groups -asynchronous -group [get_clocks clk_pl_1] -group [get_clocks wr_pll0_clk0] -group [get_clocks clk_125m_pllref]
set_clock_groups -asynchronous -group [get_clocks clk_pl_1] -group [get_clocks clk_125m_pllref]
#set_clock_groups -asynchronous -group [get_clocks clk_20m_vcxo] -group [get_clocks clk_125m_pllref] -group [get_clocks clk_125m_gtp]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets cmp_ibufds_clk_200/O]
......@@ -108,7 +108,6 @@ architecture arch of damc_fmc2zup_ref_top is
signal clk_sys_62m5 : std_logic;
-- 125MHz ref clock output
signal clk_ref_125m : std_logic;
signal clk_125m_pci : std_logic;
-- active low reset outputs, synchronous to 62m5 and 125m clocks
signal rst_sys_62m5_n : std_logic;
signal rst_ref_125m_n : std_logic;
......@@ -347,7 +346,6 @@ begin
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_125m_pci_i => '0',
-- 62.5MHz sys clock output
clk_sys_62m5_o => clk_sys_62m5,
-- 125MHz ref clock output
......
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