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Commit 8b6f09f5 authored by Imre Pechan's avatar Imre Pechan
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fix: add missing file and fix timing error

parent f6be2e44
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top/damc-fmc2zup_ref_design/Manifest.py
+ 1
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View file @ 8b6f09f5
......@@ -3,6 +3,7 @@ fetchto = "../../ip_cores"
files = [
"damc_fmc2zup_ref_top.vhd",
"damc_fmc2zup_ref_top.xdc",
"damc_fmc2zup_ref_timing.xdc"
]
modules = {
......
top/damc-fmc2zup_ref_design/damc_fmc2zup_ref_timing.xdc
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− 0
View file @ 8b6f09f5
......@@ -11,3 +11,5 @@ create_clock -name clk_200 -period 5 [get_ports clk_200_p]
set_false_path -to [get_pins {cmp_xwrc_board_damc_fmc2zup/cmp_board_common/cmp_xwr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/gen_straight.clk_i_d0_reg/D}]
set_false_path -to [get_pins {cmp_xwrc_board_damc_fmc2zup/cmp_board_common/cmp_xwr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/gen_straight.clk_i_d0_reg/D}]
set_false_path -to [get_pins {cmp_xwrc_board_damc_fmc2zup/cmp_board_common/cmp_xwr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/U_sync_tag_strobe/sync_posedge.sync0_reg/D}]
set_clock_groups -asynchronous -group [get_clocks clk_pl_1] -group [get_clocks clk_125m_pllref]
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