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White Rabbit core collection
Commits
675cfc73
Commit
675cfc73
authored
12 years ago
by
Grzegorz Daniluk
Browse files
Options
Downloads
Patches
Plain Diff
greg_counters: events from rx crc size check
parent
51e21c7d
Branches
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Changes
2
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2 changed files
modules/wr_endpoint/ep_rx_crc_size_check.vhd
+30
-27
30 additions, 27 deletions
modules/wr_endpoint/ep_rx_crc_size_check.vhd
modules/wr_endpoint/ep_rx_path.vhd
+102
-96
102 additions, 96 deletions
modules/wr_endpoint/ep_rx_path.vhd
with
132 additions
and
123 deletions
modules/wr_endpoint/ep_rx_crc_size_check.vhd
+
30
−
27
View file @
675cfc73
...
@@ -25,8 +25,11 @@ entity ep_rx_crc_size_check is
...
@@ -25,8 +25,11 @@ entity ep_rx_crc_size_check is
src_fab_o
:
out
t_ep_internal_fabric
;
src_fab_o
:
out
t_ep_internal_fabric
;
src_dreq_i
:
in
std_logic
;
src_dreq_i
:
in
std_logic
;
rmon_o
:
inout
t_rmon_triggers
;
regs_i
:
in
t_ep_out_registers
;
regs_i
:
in
t_ep_out_registers
rmon_pcs_err_o
:
out
std_logic
;
rmon_giant_o
:
out
std_logic
;
rmon_runt_o
:
out
std_logic
;
rmon_crc_err_o
:
out
std_logic
);
);
end
ep_rx_crc_size_check
;
end
ep_rx_crc_size_check
;
...
@@ -204,10 +207,10 @@ begin -- behavioral
...
@@ -204,10 +207,10 @@ begin -- behavioral
state
<=
ST_WAIT_FRAME
;
state
<=
ST_WAIT_FRAME
;
rmon_
o
.
rx_
pcs_err
<=
'0'
;
rmon_pcs_err
_o
<=
'0'
;
rmon_
o
.
rx_
giant
<=
'0'
;
rmon_giant
_o
<=
'0'
;
rmon_
o
.
rx_
runt
<=
'0'
;
rmon_runt
_o
<=
'0'
;
rmon_
o
.
rx_
crc_err
<=
'0'
;
rmon_crc_err
_o
<=
'0'
;
src_fab_o
.
sof
<=
'0'
;
src_fab_o
.
sof
<=
'0'
;
dvalid_mask
<=
"11"
;
dvalid_mask
<=
"11"
;
...
@@ -215,17 +218,17 @@ begin -- behavioral
...
@@ -215,17 +218,17 @@ begin -- behavioral
else
else
case
state
is
case
state
is
when
ST_WAIT_FRAME
=>
when
ST_WAIT_FRAME
=>
dvalid_mask
<=
"11"
;
dvalid_mask
<=
"11"
;
q_flush
<=
'0'
;
q_flush
<=
'0'
;
q_purge
<=
'0'
;
q_purge
<=
'0'
;
rmon_
o
.
rx_
pcs_err
<=
'0'
;
rmon_pcs_err
_o
<=
'0'
;
rmon_
o
.
rx_
giant
<=
'0'
;
rmon_giant
_o
<=
'0'
;
rmon_
o
.
rx_
runt
<=
'0'
;
rmon_runt
_o
<=
'0'
;
rmon_
o
.
rx_
crc_err
<=
'0'
;
rmon_crc_err
_o
<=
'0'
;
q_bytesel
<=
'0'
;
q_bytesel
<=
'0'
;
src_fab_o
.
eof
<=
'0'
;
src_fab_o
.
eof
<=
'0'
;
src_fab_o
.
error
<=
'0'
;
src_fab_o
.
error
<=
'0'
;
src_fab_o
.
sof
<=
'0'
;
src_fab_o
.
sof
<=
'0'
;
if
(
snk_fab_i
.
sof
=
'1'
)
then
if
(
snk_fab_i
.
sof
=
'1'
)
then
state
<=
ST_DATA
;
state
<=
ST_DATA
;
...
@@ -242,10 +245,10 @@ begin -- behavioral
...
@@ -242,10 +245,10 @@ begin -- behavioral
if
(
snk_fab_i
.
error
=
'1'
)
then
-- an error from the source?
if
(
snk_fab_i
.
error
=
'1'
)
then
-- an error from the source?
src_fab_o
.
error
<=
'1'
;
src_fab_o
.
error
<=
'1'
;
rmon_
o
.
rx_
pcs_err
<=
'1'
;
rmon_pcs_err
_o
<=
'1'
;
state
<=
ST_WAIT_FRAME
;
state
<=
ST_WAIT_FRAME
;
q_purge
<=
'1'
;
q_purge
<=
'1'
;
elsif
(
snk_fab_i
.
eof
=
'1'
or
snk_fab_i
.
addr
=
c_WRF_OOB
)
then
elsif
(
snk_fab_i
.
eof
=
'1'
or
snk_fab_i
.
addr
=
c_WRF_OOB
)
then
if
(
size_check_ok
=
'0'
or
crc_match
=
'0'
)
then
-- bad frame?
if
(
size_check_ok
=
'0'
or
crc_match
=
'0'
)
then
-- bad frame?
...
@@ -262,16 +265,16 @@ begin -- behavioral
...
@@ -262,16 +265,16 @@ begin -- behavioral
dvalid_mask
<=
"00"
;
dvalid_mask
<=
"00"
;
end
if
;
end
if
;
rmon_
o
.
rx_
runt
<=
is_runt
and
(
not
regs_i
.
rfcr_a_runt_o
);
rmon_runt
_o
<=
is_runt
and
(
not
regs_i
.
rfcr_a_runt_o
);
rmon_
o
.
rx_
giant
<=
is_giant
and
(
not
regs_i
.
rfcr_a_giant_o
);
rmon_giant
_o
<=
is_giant
and
(
not
regs_i
.
rfcr_a_giant_o
);
rmon_
o
.
rx_
crc_err
<=
not
crc_match
;
rmon_crc_err
_o
<=
not
crc_match
;
end
if
;
end
if
;
when
ST_OOB
=>
when
ST_OOB
=>
rmon_
o
.
rx_
runt
<=
'0'
;
rmon_runt
_o
<=
'0'
;
rmon_
o
.
rx_
giant
<=
'0'
;
rmon_giant
_o
<=
'0'
;
rmon_
o
.
rx_
crc_err
<=
'0'
;
rmon_crc_err
_o
<=
'0'
;
if
(
q_dvalid_out
=
'1'
)
then
if
(
q_dvalid_out
=
'1'
)
then
dvalid_mask
<=
dvalid_mask
(
0
)
&
'1'
;
dvalid_mask
<=
dvalid_mask
(
0
)
&
'1'
;
...
...
This diff is collapsed.
Click to expand it.
modules/wr_endpoint/ep_rx_path.vhd
+
102
−
96
View file @
675cfc73
...
@@ -6,7 +6,7 @@
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Created : 2009-06-22
-- Last update: 201
2
-0
8-29
-- Last update: 201
3
-0
3-12
-- Platform : FPGA-generic
-- Platform : FPGA-generic
-- Standard : VHDL'93
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
...
@@ -112,37 +112,37 @@ architecture behavioral of ep_rx_path is
...
@@ -112,37 +112,37 @@ architecture behavioral of ep_rx_path is
generic
(
generic
(
g_with_rtu
:
boolean
);
g_with_rtu
:
boolean
);
port
(
port
(
clk_sys_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
snk_fab_i
:
in
t_ep_internal_fabric
;
snk_fab_i
:
in
t_ep_internal_fabric
;
snk_dreq_o
:
out
std_logic
;
snk_dreq_o
:
out
std_logic
;
src_fab_o
:
out
t_ep_internal_fabric
;
src_fab_o
:
out
t_ep_internal_fabric
;
src_dreq_i
:
in
std_logic
;
src_dreq_i
:
in
std_logic
;
mbuf_is_pause_i
:
in
std_logic
;
mbuf_is_pause_i
:
in
std_logic
;
vlan_class_i
:
in
std_logic_vector
(
2
downto
0
);
vlan_class_i
:
in
std_logic_vector
(
2
downto
0
);
vlan_vid_i
:
in
std_logic_vector
(
11
downto
0
);
vlan_vid_i
:
in
std_logic_vector
(
11
downto
0
);
vlan_tag_done_i
:
in
std_logic
;
vlan_tag_done_i
:
in
std_logic
;
vlan_is_tagged_i
:
in
std_logic
;
vlan_is_tagged_i
:
in
std_logic
;
rtu_rq_o
:
out
t_ep_internal_rtu_request
;
rtu_rq_o
:
out
t_ep_internal_rtu_request
;
rtu_full_i
:
in
std_logic
;
rtu_full_i
:
in
std_logic
;
rtu_rq_valid_o
:
out
std_logic
);
rtu_rq_valid_o
:
out
std_logic
);
end
component
;
end
component
;
component
ep_rx_early_address_match
component
ep_rx_early_address_match
port
(
port
(
clk_sys_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
clk_rx_i
:
in
std_logic
;
clk_rx_i
:
in
std_logic
;
rst_n_sys_i
:
in
std_logic
;
rst_n_sys_i
:
in
std_logic
;
rst_n_rx_i
:
in
std_logic
;
rst_n_rx_i
:
in
std_logic
;
snk_fab_i
:
in
t_ep_internal_fabric
;
snk_fab_i
:
in
t_ep_internal_fabric
;
src_fab_o
:
out
t_ep_internal_fabric
;
src_fab_o
:
out
t_ep_internal_fabric
;
match_done_o
:
out
std_logic
;
match_done_o
:
out
std_logic
;
match_is_hp_o
:
out
std_logic
;
match_is_hp_o
:
out
std_logic
;
match_is_pause_o
:
out
std_logic
;
match_is_pause_o
:
out
std_logic
;
match_pause_quanta_o
:
out
std_logic_vector
(
15
downto
0
);
match_pause_quanta_o
:
out
std_logic_vector
(
15
downto
0
);
match_pause_prio_mask_o
:
out
std_logic_vector
(
7
downto
0
);
match_pause_prio_mask_o
:
out
std_logic_vector
(
7
downto
0
);
match_pause_p_o
:
out
std_logic
;
match_pause_p_o
:
out
std_logic
;
regs_i
:
in
t_ep_out_registers
);
regs_i
:
in
t_ep_out_registers
);
end
component
;
end
component
;
component
ep_clock_alignment_fifo
component
ep_clock_alignment_fifo
...
@@ -178,19 +178,19 @@ architecture behavioral of ep_rx_path is
...
@@ -178,19 +178,19 @@ architecture behavioral of ep_rx_path is
component
ep_rx_vlan_unit
component
ep_rx_vlan_unit
port
(
port
(
clk_sys_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
snk_fab_i
:
in
t_ep_internal_fabric
;
snk_fab_i
:
in
t_ep_internal_fabric
;
snk_dreq_o
:
out
std_logic
;
snk_dreq_o
:
out
std_logic
;
src_fab_o
:
out
t_ep_internal_fabric
;
src_fab_o
:
out
t_ep_internal_fabric
;
src_dreq_i
:
in
std_logic
;
src_dreq_i
:
in
std_logic
;
tclass_o
:
out
std_logic_vector
(
2
downto
0
);
tclass_o
:
out
std_logic_vector
(
2
downto
0
);
vid_o
:
out
std_logic_vector
(
11
downto
0
);
vid_o
:
out
std_logic_vector
(
11
downto
0
);
tag_done_o
:
out
std_logic
;
tag_done_o
:
out
std_logic
;
is_tagged_o
:
out
std_logic
;
is_tagged_o
:
out
std_logic
;
rmon_o
:
inout
t_rmon_triggers
;
rmon_o
:
inout
t_rmon_triggers
;
regs_i
:
in
t_ep_out_registers
;
regs_i
:
in
t_ep_out_registers
;
regs_o
:
out
t_ep_in_registers
);
regs_o
:
out
t_ep_in_registers
);
end
component
;
end
component
;
component
ep_rx_oob_insert
component
ep_rx_oob_insert
...
@@ -206,14 +206,17 @@ architecture behavioral of ep_rx_path is
...
@@ -206,14 +206,17 @@ architecture behavioral of ep_rx_path is
component
ep_rx_crc_size_check
component
ep_rx_crc_size_check
port
(
port
(
clk_sys_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
snk_fab_i
:
in
t_ep_internal_fabric
;
snk_fab_i
:
in
t_ep_internal_fabric
;
snk_dreq_o
:
out
std_logic
;
snk_dreq_o
:
out
std_logic
;
src_fab_o
:
out
t_ep_internal_fabric
;
src_fab_o
:
out
t_ep_internal_fabric
;
src_dreq_i
:
in
std_logic
;
src_dreq_i
:
in
std_logic
;
rmon_o
:
inout
t_rmon_triggers
;
regs_i
:
in
t_ep_out_registers
;
regs_i
:
in
t_ep_out_registers
);
rmon_pcs_err_o
:
out
std_logic
;
rmon_giant_o
:
out
std_logic
;
rmon_runt_o
:
out
std_logic
;
rmon_crc_err_o
:
out
std_logic
);
end
component
;
end
component
;
component
ep_rx_wb_master
component
ep_rx_wb_master
...
@@ -238,7 +241,7 @@ architecture behavioral of ep_rx_path is
...
@@ -238,7 +241,7 @@ architecture behavioral of ep_rx_path is
src_fab_o
:
out
t_ep_internal_fabric
;
src_fab_o
:
out
t_ep_internal_fabric
;
src_dreq_i
:
in
std_logic
;
src_dreq_i
:
in
std_logic
;
mbuf_valid_i
:
in
std_logic
;
mbuf_valid_i
:
in
std_logic
;
mbuf_ack_o
:
out
std_logic
;
mbuf_ack_o
:
out
std_logic
;
mbuf_drop_i
:
in
std_logic
;
mbuf_drop_i
:
in
std_logic
;
mbuf_pclass_i
:
in
std_logic_vector
(
7
downto
0
);
mbuf_pclass_i
:
in
std_logic_vector
(
7
downto
0
);
mbuf_is_hp_i
:
in
std_logic
;
mbuf_is_hp_i
:
in
std_logic
;
...
@@ -295,24 +298,24 @@ architecture behavioral of ep_rx_path is
...
@@ -295,24 +298,24 @@ architecture behavioral of ep_rx_path is
signal
fab_pipe
:
t_fab_pipe
(
0
to
9
);
signal
fab_pipe
:
t_fab_pipe
(
0
to
9
);
signal
dreq_pipe
:
std_logic_vector
(
9
downto
0
);
signal
dreq_pipe
:
std_logic_vector
(
9
downto
0
);
signal
ematch_done
:
std_logic
;
signal
ematch_done
:
std_logic
;
signal
ematch_is_hp
:
std_logic
;
signal
ematch_is_hp
:
std_logic
;
signal
ematch_is_pause
:
std_logic
;
signal
ematch_is_pause
:
std_logic
;
signal
pfilter_pclass
:
std_logic_vector
(
7
downto
0
);
signal
pfilter_pclass
:
std_logic_vector
(
7
downto
0
);
signal
pfilter_drop
:
std_logic
;
signal
pfilter_drop
:
std_logic
;
signal
pfilter_done
:
std_logic
;
signal
pfilter_done
:
std_logic
;
signal
vlan_tclass
:
std_logic_vector
(
2
downto
0
);
signal
vlan_tclass
:
std_logic_vector
(
2
downto
0
);
signal
vlan_vid
:
std_logic_vector
(
11
downto
0
);
signal
vlan_vid
:
std_logic_vector
(
11
downto
0
);
signal
vlan_tag_done
:
std_logic
;
signal
vlan_tag_done
:
std_logic
;
signal
vlan_is_tagged
:
std_logic
;
signal
vlan_is_tagged
:
std_logic
;
signal
pcs_fifo_almostfull
:
std_logic
;
signal
pcs_fifo_almostfull
:
std_logic
;
signal
mbuf_rd
,
mbuf_valid
,
mbuf_we
,
mbuf_pf_drop
,
mbuf_is_hp
:
std_logic
;
signal
mbuf_rd
,
mbuf_valid
,
mbuf_we
,
mbuf_pf_drop
,
mbuf_is_hp
:
std_logic
;
signal
mbuf_is_pause
,
mbuf_full
,
mbuf_we_d0
,
mbuf_we_d1
:
std_logic
;
signal
mbuf_is_pause
,
mbuf_full
,
mbuf_we_d0
,
mbuf_we_d1
:
std_logic
;
signal
mbuf_pf_class
:
std_logic_vector
(
7
downto
0
);
signal
mbuf_pf_class
:
std_logic_vector
(
7
downto
0
);
begin
-- behavioral
begin
-- behavioral
fab_pipe
(
0
)
<=
pcs_fab_i
;
fab_pipe
(
0
)
<=
pcs_fab_i
;
...
@@ -412,39 +415,42 @@ begin -- behavioral
...
@@ -412,39 +415,42 @@ begin -- behavioral
U_crc_size_checker
:
ep_rx_crc_size_check
U_crc_size_checker
:
ep_rx_crc_size_check
port
map
(
port
map
(
clk_sys_i
=>
clk_sys_i
,
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_sys_i
,
rst_n_i
=>
rst_n_sys_i
,
snk_fab_i
=>
fab_pipe
(
4
),
snk_fab_i
=>
fab_pipe
(
4
),
snk_dreq_o
=>
dreq_pipe
(
4
),
snk_dreq_o
=>
dreq_pipe
(
4
),
src_dreq_i
=>
dreq_pipe
(
5
),
src_dreq_i
=>
dreq_pipe
(
5
),
src_fab_o
=>
fab_pipe
(
5
),
src_fab_o
=>
fab_pipe
(
5
),
rmon_o
=>
rmon_o
,
regs_i
=>
regs_i
,
regs_i
=>
regs_i
);
rmon_pcs_err_o
=>
rmon_o
.
rx_pcs_err
,
rmon_giant_o
=>
rmon_o
.
rx_giant
,
rmon_runt_o
=>
rmon_o
.
rx_runt
,
rmon_crc_err_o
=>
rmon_o
.
rx_crc_err
);
gen_with_vlan_unit
:
if
(
g_with_vlans
)
generate
gen_with_vlan_unit
:
if
(
g_with_vlans
)
generate
U_vlan_unit
:
ep_rx_vlan_unit
U_vlan_unit
:
ep_rx_vlan_unit
port
map
(
port
map
(
clk_sys_i
=>
clk_sys_i
,
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_sys_i
,
rst_n_i
=>
rst_n_sys_i
,
snk_fab_i
=>
fab_pipe
(
5
),
snk_fab_i
=>
fab_pipe
(
5
),
snk_dreq_o
=>
dreq_pipe
(
5
),
snk_dreq_o
=>
dreq_pipe
(
5
),
src_fab_o
=>
fab_pipe
(
6
),
src_fab_o
=>
fab_pipe
(
6
),
src_dreq_i
=>
dreq_pipe
(
6
),
src_dreq_i
=>
dreq_pipe
(
6
),
tclass_o
=>
vlan_tclass
,
tclass_o
=>
vlan_tclass
,
vid_o
=>
vlan_vid
,
vid_o
=>
vlan_vid
,
tag_done_o
=>
vlan_tag_done
,
tag_done_o
=>
vlan_tag_done
,
is_tagged_o
=>
vlan_is_tagged
,
is_tagged_o
=>
vlan_is_tagged
,
rmon_o
=>
rmon_o
,
rmon_o
=>
rmon_o
,
regs_i
=>
regs_i
,
regs_i
=>
regs_i
,
regs_o
=>
regs_o
);
regs_o
=>
regs_o
);
end
generate
gen_with_vlan_unit
;
end
generate
gen_with_vlan_unit
;
gen_without_vlan_unit
:
if
(
not
g_with_vlans
)
generate
gen_without_vlan_unit
:
if
(
not
g_with_vlans
)
generate
fab_pipe
(
6
)
<=
fab_pipe
(
5
);
fab_pipe
(
6
)
<=
fab_pipe
(
5
);
dreq_pipe
(
5
)
<=
dreq_pipe
(
6
);
dreq_pipe
(
5
)
<=
dreq_pipe
(
6
);
vlan_tclass
<=
(
others
=>
'0'
);
vlan_tclass
<=
(
others
=>
'0'
);
vlan_vid
<=
(
others
=>
'0'
);
vlan_vid
<=
(
others
=>
'0'
);
vlan_tag_done
<=
'0'
;
vlan_tag_done
<=
'0'
;
vlan_is_tagged
<=
'0'
;
vlan_is_tagged
<=
'0'
;
end
generate
gen_without_vlan_unit
;
end
generate
gen_without_vlan_unit
;
...
@@ -453,24 +459,24 @@ begin -- behavioral
...
@@ -453,24 +459,24 @@ begin -- behavioral
generic
map
(
generic
map
(
g_with_rtu
=>
g_with_rtu
)
g_with_rtu
=>
g_with_rtu
)
port
map
(
port
map
(
clk_sys_i
=>
clk_sys_i
,
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_sys_i
,
rst_n_i
=>
rst_n_sys_i
,
snk_fab_i
=>
fab_pipe
(
6
),
snk_fab_i
=>
fab_pipe
(
6
),
snk_dreq_o
=>
dreq_pipe
(
6
),
snk_dreq_o
=>
dreq_pipe
(
6
),
src_fab_o
=>
fab_pipe
(
7
),
src_fab_o
=>
fab_pipe
(
7
),
src_dreq_i
=>
dreq_pipe
(
7
),
src_dreq_i
=>
dreq_pipe
(
7
),
mbuf_is_pause_i
=>
mbuf_is_pause
,
-- this module is in the pipe before ep_rx_status_reg_insert,
mbuf_is_pause_i
=>
mbuf_is_pause
,
-- this module is in the pipe before ep_rx_status_reg_insert,
-- however, we know that mbuf_is_pause is valid when it
-- however, we know that mbuf_is_pause is valid when it
-- is used by this module -- this is because blocks the pipe
-- is used by this module -- this is because blocks the pipe
-- untill mbuf_valid is HIGH, and rtu_rq_valid_o is inserted HIGH
-- untill mbuf_valid is HIGH, and rtu_rq_valid_o is inserted HIGH
-- at the end of the header... (clear ??:)
-- at the end of the header... (clear ??:)
vlan_class_i
=>
vlan_tclass
,
vlan_class_i
=>
vlan_tclass
,
vlan_vid_i
=>
vlan_vid
,
vlan_vid_i
=>
vlan_vid
,
vlan_tag_done_i
=>
vlan_tag_done
,
vlan_tag_done_i
=>
vlan_tag_done
,
vlan_is_tagged_i
=>
vlan_is_tagged
,
vlan_is_tagged_i
=>
vlan_is_tagged
,
rtu_rq_o
=>
rtu_rq_o
,
rtu_rq_o
=>
rtu_rq_o
,
rtu_full_i
=>
rtu_full_i
,
rtu_full_i
=>
rtu_full_i
,
rtu_rq_valid_o
=>
rtu_rq_valid_o
);
rtu_rq_valid_o
=>
rtu_rq_valid_o
);
U_Gen_Status
:
ep_rx_status_reg_insert
U_Gen_Status
:
ep_rx_status_reg_insert
port
map
(
port
map
(
...
...
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